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An 18-bit sigma–delta switched-capacitor modulator using 4-order single-loop CIFB architecture

Guiping Cao and Ning Dong ,

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Abstract: Oversampling sigma–delta (Σ–Δ) analog-to-digital converters (ADCs) are currently one of the most widely used architectures for high-resolution ADCs. The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed. Structurally, the Σ–Δ ADC is divided into two parts: a front-end analog modulator and a back-end digital filter. The performance of the front-end analog modulator has a marked influence on the entire Σ–Δ ADC system. In this paper, a 4-order single-loop switched-capacitor modulator with a CIFB (cascade-of-integrators feed-back) structure is proposed. Based on the chosen modulator architecture, the ASIC circuit is implemented using a Chartered 0.35 μm CMOS process with a chip area of 1.72 × 0.75 mm2. The chip operates with a 3.3-V power supply and a power dissipation of 22 mW. According to the results, the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits (ENOB) was almost 18-bit.

Key words: sigma–delta modulatoroversamplingCIFB structureswitched-capacitor

Abstract: Oversampling sigma–delta (Σ–Δ) analog-to-digital converters (ADCs) are currently one of the most widely used architectures for high-resolution ADCs. The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed. Structurally, the Σ–Δ ADC is divided into two parts: a front-end analog modulator and a back-end digital filter. The performance of the front-end analog modulator has a marked influence on the entire Σ–Δ ADC system. In this paper, a 4-order single-loop switched-capacitor modulator with a CIFB (cascade-of-integrators feed-back) structure is proposed. Based on the chosen modulator architecture, the ASIC circuit is implemented using a Chartered 0.35 μm CMOS process with a chip area of 1.72 × 0.75 mm2. The chip operates with a 3.3-V power supply and a power dissipation of 22 mW. According to the results, the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits (ENOB) was almost 18-bit.

Key words: sigma–delta modulatoroversamplingCIFB structureswitched-capacitor



References:

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Candy J C, Benjamin O J. The structure of quantization noise from sigma-delta modulation. IEEE Trans Commun, 1981, 29(9), 1316

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Candy J C. A use of double integration in sigma-delta modulations. IEEE Trans Commun, 1985, 33(3), 249

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Candy J C, Huynh A. Double Interpolation for digital-to-analog conversion. IEEE Trans Commun, 1986, 34(1), 77

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Hayashi T, Inabe Y, Uchimura K, et al. A multistage delta-sigma modulator without double integration loop. ISSCC Digest of Technical Papers, 1986, 182

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Chen J Q, Ren J Y, Xun J, et al. An 80 dB dynamic range modulator for a GSM system. Chin J Semicond, 2007, 28(2), 294

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Cao Y, Ren T L, Hong Z L, et al. A 16 bit 96 kHz chopper-stabilized sigma-delta ADC. Chin J Semicond, 2007, 28(8), 1204

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Yuan J, Zhang Z F, Wu J, et al. Continuous time sigma delta ADC design and non-idealities analysis. J Semicond, 2011, 32(12), 125007

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Li R, Li J, Yi T, et al. A 18-mW, 20-MHz bandwidth, 12-bit continuous-time modulator using a power-efficient multi-stage amplifier. J Semicond, 2012, 33(1), 015007

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Caldwell T C, Johns D A. An 8-th order MASH delta-sigma with an OSR of 3. ESSCIRC, 2009, 476

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Chiang J S, Chen H L, Chou P C. A 2.5-V 14-bit MASH sigma-delta modulator for ADSL. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 2004, 24

[15]

Yao L, Steyaert M, Sansen W M. Low-power low-voltage sigma-delta modulators in nanometer CMOS. Springer Science & Business Media, 2006

[16]

Chao K C, Nadeem S, Lee W L, et al. A higher order topology for interpolative modulators for oversampling A/D converters. IEEE Trans Circuits Syst, 1990, 37(3), 309

[17]

Cao G. Study and ASIC implementation of high-resolution sigma-delta modulator. PhD Thesis, University of Science and Technology of China, 2012

[18]

Wang F, Harjani R. Power analysis and optimal design of opamps for oversampled converters. IEEE Trans Circuits Syst II, 1999, 46, 359

[19]

Medeiro Hidalgo F, Pérez Verdú B, Rosa Utrera J M, et al. Fourth-order cascade SC sigma delta modulator: a comparative study. IEEE Trans Circuits Syst I, 1998, 45(10), 1041

[20]

Ericson M N. High-temperature, high-resolution A/D conversion using 2nd and 4th-order sigma delta modulation in 3.3 V 0.5 ?m SOS-CMOS. PhD Thesis, University of Tennessee, 2002

[21]

Geets Y, et al. A 2.5 M sample/s multi-bit sigma delta CMOS ADC with 95 dB SN. Digest of Technical Papers, Solid-State Circuits Conference, 2000, 336

[22]

Balmelli P, Huang Q. A 25 MS/s 14 b 200 mW Σ? modulator in 0.18 ?m cmos. ISSCC Dig Tech Papers, 2005, 74

[23]

Brigati S, et al. A Fourth-order singla-bit switched capacitor sigma delta modulator for distributed sensor applications. IEEE Trans Instrum Meas, 2004, 53(2), 266

[24]

Gerosa A, Neviani A. A 1.8 ?W sigma delta modulator for 8-bit digitization of cardiac signals in implantable pacemakers operating down to 1.8 V. IEEE Trans Circuits Syst II, 2005, 52(2), 71

[25]

Yao L, Steyaert M, Sansen W. A 1-V, 1 MS/s, 88-dB sigma delta modulator in 0.13-?m digital CMOS technology. Symposium on VLSI Circuits Digest of Technical, 2005, 180

[26]

Chen L. High precision Σ? ADC. PhD Thesis, Northwestern Polytechnical University, 2006

[1]

Inose H, Inose H, Yasuda Y, Murakami J. A telemetering system by code modulation- modulation. IRE Trans Space Electron Telemetry, 1962, 8, 204

[2]

Ritchie G R, Candy J, Ninke W. Interpolative digital to analog converters. IEEE Trans Commun, 1974, 22, 1797

[3]

Candy J C. A use of limit cycle oscillations to obtain robust analog-to-digital converters. IEEE Trans Commun, 1974, 22(3), 298

[4]

Candy J C, Wooley B, Benjamin O. A voiceband codec with digital filtering. IEEE Trans Commun, 1981, 29(6), 815

[5]

Candy J C, Benjamin O J. The structure of quantization noise from sigma-delta modulation. IEEE Trans Commun, 1981, 29(9), 1316

[6]

Candy J C. A use of double integration in sigma-delta modulations. IEEE Trans Commun, 1985, 33(3), 249

[7]

Candy J C, Huynh A. Double Interpolation for digital-to-analog conversion. IEEE Trans Commun, 1986, 34(1), 77

[8]

Hayashi T, Inabe Y, Uchimura K, et al. A multistage delta-sigma modulator without double integration loop. ISSCC Digest of Technical Papers, 1986, 182

[9]

Chen J Q, Ren J Y, Xun J, et al. An 80 dB dynamic range modulator for a GSM system. Chin J Semicond, 2007, 28(2), 294

[10]

Cao Y, Ren T L, Hong Z L, et al. A 16 bit 96 kHz chopper-stabilized sigma-delta ADC. Chin J Semicond, 2007, 28(8), 1204

[11]

Yuan J, Zhang Z F, Wu J, et al. Continuous time sigma delta ADC design and non-idealities analysis. J Semicond, 2011, 32(12), 125007

[12]

Li R, Li J, Yi T, et al. A 18-mW, 20-MHz bandwidth, 12-bit continuous-time modulator using a power-efficient multi-stage amplifier. J Semicond, 2012, 33(1), 015007

[13]

Caldwell T C, Johns D A. An 8-th order MASH delta-sigma with an OSR of 3. ESSCIRC, 2009, 476

[14]

Chiang J S, Chen H L, Chou P C. A 2.5-V 14-bit MASH sigma-delta modulator for ADSL. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 2004, 24

[15]

Yao L, Steyaert M, Sansen W M. Low-power low-voltage sigma-delta modulators in nanometer CMOS. Springer Science & Business Media, 2006

[16]

Chao K C, Nadeem S, Lee W L, et al. A higher order topology for interpolative modulators for oversampling A/D converters. IEEE Trans Circuits Syst, 1990, 37(3), 309

[17]

Cao G. Study and ASIC implementation of high-resolution sigma-delta modulator. PhD Thesis, University of Science and Technology of China, 2012

[18]

Wang F, Harjani R. Power analysis and optimal design of opamps for oversampled converters. IEEE Trans Circuits Syst II, 1999, 46, 359

[19]

Medeiro Hidalgo F, Pérez Verdú B, Rosa Utrera J M, et al. Fourth-order cascade SC sigma delta modulator: a comparative study. IEEE Trans Circuits Syst I, 1998, 45(10), 1041

[20]

Ericson M N. High-temperature, high-resolution A/D conversion using 2nd and 4th-order sigma delta modulation in 3.3 V 0.5 ?m SOS-CMOS. PhD Thesis, University of Tennessee, 2002

[21]

Geets Y, et al. A 2.5 M sample/s multi-bit sigma delta CMOS ADC with 95 dB SN. Digest of Technical Papers, Solid-State Circuits Conference, 2000, 336

[22]

Balmelli P, Huang Q. A 25 MS/s 14 b 200 mW Σ? modulator in 0.18 ?m cmos. ISSCC Dig Tech Papers, 2005, 74

[23]

Brigati S, et al. A Fourth-order singla-bit switched capacitor sigma delta modulator for distributed sensor applications. IEEE Trans Instrum Meas, 2004, 53(2), 266

[24]

Gerosa A, Neviani A. A 1.8 ?W sigma delta modulator for 8-bit digitization of cardiac signals in implantable pacemakers operating down to 1.8 V. IEEE Trans Circuits Syst II, 2005, 52(2), 71

[25]

Yao L, Steyaert M, Sansen W. A 1-V, 1 MS/s, 88-dB sigma delta modulator in 0.13-?m digital CMOS technology. Symposium on VLSI Circuits Digest of Technical, 2005, 180

[26]

Chen L. High precision Σ? ADC. PhD Thesis, Northwestern Polytechnical University, 2006

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History

Manuscript received: 25 October 2019 Manuscript revised: 08 December 2019 Online: Accepted Manuscript: 24 February 2020 Uncorrected proof: 12 March 2020

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