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Volume 34, Issue 4, Apr 2013


  • One-phonon resonant electron Raman scattering in multilayer coaxial cylindrical AlxGa1-xAs/GaAs quantum cables

    Qinghu Zhong, Xuehua Yi, Shouliang Pu, Yuzhen Yan

    J. Semicond.  2013, 34(4): 042001

    doi: 10.1088/1674-4926/34/4/042001

    Abstract Full Text PDF Get Citation

    We have presented a theoretical calculation of the differential cross section (DCS) for the electron Raman scattering (ERS) process associated with the interface optical (IO) and surface optical (SO) phonons in multilayer coaxial cylindrical AlxGa1-xAs/GaAs quantum cables (QC). We consider the Fr?hlich electron-phonon interaction in the framework of the dielectric continuum approach. The selection rules for the processes are studied. Singularities are found to be sensitively size-dependent and by varying the size of the QC, it is possible to control the frequency shift in the Raman spectra. A discussion of the phonon behavior for the QC with different size is presented. The numerical results are also compared with those of experiments.


  • Elaboration and characterization of a KCl single crystal doped with nanocrystalsof a Sb2O3 semiconductor

    L. Bouhdjer, S. Addala, A. Chala, O. Halimi, B. Boudine, M. Sebais

    J. Semicond.  2013, 34(4): 043001

    doi: 10.1088/1674-4926/34/4/043001

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    Undoped and doped KCl single crystals have been successfully elaborated via the Czochralski (Cz) method. The effects of dopant Sb2O3 nanocrystals on structural and optical properties were investigated by a number of techniques, including X-ray diffraction (XRD), scanning electron microscopy (SEM), energy dispersive X-ray (EDAX) analysis, UV-visible and photoluminescence (PL) spectrophotometers. An XRD pattern of KCl:Sb2O3 reveals that the Sb2O3 nanocrystals are in the well-crystalline orthorhombic phase. The broadening of diffraction peaks indicated the presence of a Sb2O3 semiconductor in the nanometer size regime. The shift of absorption and PL peaks is observed near 334 nm and 360 nm respectively due to the quantum confinement effect in Sb2O3 nanocrystals. Particle sizes calculated from XRD studies agree fairly well with those estimated from optical studies. An SEM image of the surface KCl:Sb2O3 single crystal shows large quasi-spherical of Sb2O3 crystallites scattered on the surface. The elemental analysis from EDAX demonstrates that the KCl:Sb2O3 single crystal is slightly rich in oxygen and a source of excessive quantities of oxygen is discussed.

  • Solar light assisted photocatalysis of water using a zinc oxide semiconductor

    S.S. Shinde, C.H. Bhosale, K.Y. Rajpure

    J. Semicond.  2013, 34(4): 043002

    doi: 10.1088/1674-4926/34/4/043002

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    The photocatalytic decomposition of an eco-persistent AO7 dye with sunlight in an oxygenated aqueous suspension has been studied under a nano-crystalline hexagonal ZnO photocatalyst. The effect of substrate temperature on the structural, morphological and photoactive properties has been investigated. The degradation of the AO7 dye is achieved using a photoelectrochemical reactor module equipped with ZnO synthesized electrodes. Kinetic parameters have been investigated in terms of a first order rate equation. The rate constant for this heterogeneous photocatalysis was evaluated as a function of the initial concentration of original species. A substantial reduction in AO7 dye is achieved as analyzed from COD and TOC studies. The mechanism for the degradation could be explained on the basis of the Langmuir-Hinshelwood mechanism.

  • Defects in CdMnTe crystals for nuclear detector applications

    Yuanyuan Du, Wanqi Jie, Yadong Xu, Xin Zheng, Tao Wang, Hui Yu

    J. Semicond.  2013, 34(4): 043003

    doi: 10.1088/1674-4926/34/4/043003

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    A laser scanning confocal microscope (LSCM) and a field-emission scanning electron microscope (FE-SEM) were used to study the defects in CdMnTe crystals, such as twin boundaries, Te inclusions, and dislocations. Twin boundaries were usually decorated with Te inclusions, which could induce dislocations. The optical, electrical properties and detector performance of CdMnTe crystals with twins and free of twins were compared. The results showed that the wafers with a high density of twins usually had lower average IR transmittance and poorer crystalline quality. Besides, the energy spectra indicated that twin boundaries in a CdMnTe detector had a negative effect on detector performance; the values of both the energy resolution and (μτ)e were nearly half of those for a single crystal detector.


  • Fabrication and characterization of a GaN/(4H)SiC vertical pn power diode using direct and interfaced epitaxial-growth approaches

    Bose Srikanta, S K Mazumder

    J. Semicond.  2013, 34(4): 044001

    doi: 10.1088/1674-4926/34/4/044001

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    We report the fabrication and characterization of a vertical pn power diode which is realized using two separate epitaxial-growth mechanisms:(a) p-GaN over p-(4H)SiC, and (b) p-GaN over n-(4H)SiC with AlN as the interface layer. In all of the cases, n+-doped (4H)SiC serves as the cathode substrate. Pd(200 ?)/Au(10000 ?) is used for the anode contact while Ni(1000 ?) is used for the bottom cathode contact. The measured forward drop of the pn diode with AlN as the interface material is found to be around 5.1 V; whereas, it is 3 V for the other sample structure. The measured reverse-blocking voltage is found to be greater than 200 V.

  • A 2DEG charge density based drain current model for various Al and In molefraction mobility dependent nano-scale AlInGaN/AlN/GaN HEMT devices

    Godwin Raj, Hemant Pardeshi, Sudhansu Kumar Pati, N Mohankumar, Chandan Kumar Sarkar

    J. Semicond.  2013, 34(4): 044002

    doi: 10.1088/1674-4926/34/4/044002

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    We present a two-dimensional electron gas (2DEG) charge-control mobility variation based drain current model for sheet carrier density in the channel. The model was developed for the AlInGaN/AlN/GaN high-electron-mobility transistor. The sheet carrier density model used here accounts for the independence between the Fermi levels Ef and ns along with mobility for various Al and In molefractions. This physics based ns model fully depends upon the variation of Ef, u0, the first subband E0, the second subband E1, and ns. We present a physics based analytical drain current model using ns with the minimum set of parameters. The analytical results obtained are compared with the experimental results for four samples with various molefraction and barrier thickness. A good agreement between the results is obtained, thus validating the model.

  • A compact charge-based model to study the nanoscale undoped double gate MOSFETs for nanoelectronic circuit design using genetic algorithms

    T. Bendib, F. Djeffal, D. Arar

    J. Semicond.  2013, 34(4): 044003

    doi: 10.1088/1674-4926/34/4/044003

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    The analytical modeling of nanoscale devices is an important area of computer-aided design for fast and accurate nanoelectronic design and optimization. In the present paper, a new approach for modeling semiconductor devices, nanoscale double gate DG MOSFETs, by use of the gradual channel approximation (GC) approach and genetic algorithm optimization technique (GA) is presented. The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction, to achieve reliable, accurate and simple compact models for nanoelectronic circuit simulations. Our compact models give good predictions of the quantum capacitance, threshold voltage shift, quantum inversion charge density and drain current. These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schr?dinger equations. The developed models can also be incorporated into nanoelectronic circuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage.

  • Motion of current filaments in avalanching PIN diodes

    Xingrong Ren, Changchun Chai, Zhenyang Ma, Yintang Yang, Liping Qiao, Chunlei Shi, Lihua Ren

    J. Semicond.  2013, 34(4): 044004

    doi: 10.1088/1674-4926/34/4/044004

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    The motion of current filaments in avalanching PIN diodes has been investigated in this paper by 2D transient numerical simulations. The simulation results show that the filament can move along the length of the PIN diode back and forth when the self-heating effect is considered. The voltage waveform varies periodically due to the motion of the filament. The filament motion is driven by the temperature gradient in the filament due to the negative temperature dependence of the impact ionization rates. Contrary to the traditional understanding that current filamentation is a potential cause of thermal destruction, it is shown in this paper that the thermally-driven motion of current filaments leads to the homogenization of temperature in the diode and is expected to have a positive influence on the failure threshold of the PIN diode.

  • Influence of gate-source/drain misalignment on the performance of bulk FinFETs by a 3D full band Monte Carlo simulation

    Juncheng Wang, Gang Du, Kangliang Wei, Lang Zeng, Xing Zhang, Xiaoyan Liu

    J. Semicond.  2013, 34(4): 044005

    doi: 10.1088/1674-4926/34/4/044005

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    We investigate the influence of gate-source/drain (G-S/D) misalignment on the performance of bulk fin field effect transistors (FinFETs) through the three-dimensional (3D) full band Monte Carlo simulator. Several scattering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.

  • An extrinsic fmax > 100 GHz InAlN/GaN HEMT with AlGaN back barrier

    Bo Liu, Zhihong Feng, Shaobo Dun, Xiongwen Zhang, Guodong Gu, Yuangang Wang, Peng Xu, Zezhao He, Shujun Cai

    J. Semicond.  2013, 34(4): 044006

    doi: 10.1088/1674-4926/34/4/044006

    Abstract Full Text PDF Get Citation

    We report the DC and RF performance of InAlN/GaN high-electron mobility transistors with AlGaN back barrier grown on SiC substrates. These presented results confirm the high performance that is reachable by InAlN-based technology. The InAlN/GaN HEMT sample showed a high 2DEG mobility of 1550 cm2/(V·s) at a 2DEG density of 1.7×1013 cm-2. DC and RF measurements were performed on the unpassivated device with 0.2 μm "T" gate. The maximum drain current density at VGS=2 V is close to 1.05 A/mm in a reproducible way. The reduction in gate leakage current helps to increase the frequency performance of AlGaN back barrier devices. The power gain cut-off frequency of a transistor with an AlGaN back barrier is 105 GHz, which is much higher than that of the device without an AlGaN back barrier at the same gate length. These results indicate InAlN/GaN HEMT is a promising candidate for millimeter-wave application.

  • A 1.55-μm laser array monolithically integrated with an MMI combiner

    Li Ma, Hongliang Zhu, Song Liang, Baojun Wang, Can Zhang, Lingjuan Zhao, Jing Bian, Minghua Chen

    J. Semicond.  2013, 34(4): 044007

    doi: 10.1088/1674-4926/34/4/044007

    Abstract Full Text PDF Get Citation

    The monolithic integration of four 1.55-μm range InGaAsP/InP distributed feedback lasers with a 4×1 multimode-interference (MMI) optical combiner using the varied width ridge method is proposed and demonstrated. The average output power is 1.5 mW when the current of LD is 100 mA and the threshold current is 30-35 mA at 25℃. The lasing wavelength is 1.55-μm range and 40 dB sidemode suppression ratio is obtained. The four channels can operate separately or simultaneously.

  • A high performance carrier stored trench bipolar transistor with a field-modified P-base region

    Yue Qi, Zhigang Wang, Wanjun Chen, Bo Zhang

    J. Semicond.  2013, 34(4): 044008

    doi: 10.1088/1674-4926/34/4/044008

    Abstract Full Text PDF Get Citation

    A novel high performance carrier stored trench bipolar transistor (CSTBT) with a field-modified P-base region is proposed. Due to the p-pillars inserted into the drift region extending the P-base region to the bottom of the trench gate, the electric field around the trench gate is modified, preventing the CSTBT from breakdown in advance caused by a concentration of the electric field at the edge of the trench gate. The p-pillars under the p-well forming the novel P-base region also provide extra paths for hole transportation. Thus, the switching time is also reduced. Simulation results have shown that the blocking voltage (BV) of the novel CSTBT is almost 430 V higher exhibiting avalanche breakdown properties compared with the conventional CSTBT. Moreover, the turn-off time of the novel structure is 0.3 μs (17%) shorter than the conventional CSTBT with the same gate length.

  • The resonance frequency shift in an SOI nano-waveguide microring resonator

    Junbin Zang, Chenyang Xue, Liping Wei, Chao Liu, Danfeng Cui, Yonghua Wang, Wendong Zhang

    J. Semicond.  2013, 34(4): 044009

    doi: 10.1088/1674-4926/34/4/044009

    Abstract Full Text PDF Get Citation

    To research the effect of a deposited SiO2 insulating layer on the resonance frequency modulation of an SOI nanowaveguide ring cavity during integration fabrication, a rib waveguide ring resonator was systematically designed and fabricated. SiO2 insulating layers with different thicknesses were deposited for analysis of the frequency shift characteristics. By testing the resonance transmission spectrum power of this structure, it is found that there are blue shifts after SiO2 deposition, and the frequency shift value of a structure with a 500 nm SiO2 insulating layer deposited is 0.8 nm, that is 0.24 THz at the resonance point where wavelength is around 1550 nm. Taking advantage of this conclusion, efficient optical modulation is available by choosing different frequency band resonance wavelengths to narrow the frequency modulation range.


  • Analysis of the dV/dt effect on an IGBT gate circuit in IPM

    Qing Hua, Zehong Li, Bo Zhang, Xiangjun Huang, Dekai Cheng

    J. Semicond.  2013, 34(4): 045001

    doi: 10.1088/1674-4926/34/4/045001

    Abstract Full Text PDF Get Citation

    The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT. The dV/dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher dV/dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on. By optimizing these parameters, the dV/dt induced voltage spike can be effectively controlled.

  • A-3 dBm RF transmitter front-end for 802.11g application

    Jinxin Zhao, Jun Yan, Yin Shi

    J. Semicond.  2013, 34(4): 045002

    doi: 10.1088/1674-4926/34/4/045002

    Abstract Full Text PDF Get Citation

    A 2.4 GHz, direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13 μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals. The front-end output power is-3 dBm while the corresponding EVM is-27 dB which is necessary for the 802.11g standard of EVM at-25 dB. With the adopted gain control strategy the output power changes from-14.3 to-3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process. A power detector indicates the output power and delivers a voltage to the baseband to control the output power.

  • A 23 GHz low power VCO in SiGe BiCMOS technology

    Yinkun Huang, Danyu Wu, Lei Zhou, Fan Jiang, Jin Wu, Zhi Jin

    J. Semicond.  2013, 34(4): 045003

    doi: 10.1088/1674-4926/34/4/045003

    Abstract Full Text PDF Get Citation

    A 23 GHz voltage controlled oscillator (VCO) with very low power consumption is presented. This paper presents the design and measurement of an integrated millimeter wave VCO. This VCO employs an on-chip inductor and MOS varactor to form a high Q resonator. The VCO RFIC was implemented in a 0.18 μm 120 GHz ft SiGe hetero-junction bipolar transistor (HBT) BiCMOS technology. The VCO oscillation frequency is around 23 GHz, targeting at the ultra wideband (UWB) and short range radar applications. The core of the VCO circuit consumes 1 mA current from a 2.5 V power supply and the VCO phase noise was measured at around-94 dBc/Hz at a 1 MHz frequency offset. The FOM of the VCO is-177 dBc/Hz.

  • New de-embedding structures for extracting the electrical parameters of a through-silicon-via pair

    Jing Zhou, Lixi Wan, Jun Li, Huijuan Wang, Fengwei Dai, Daniel Guidotti, Liqiang Cao, Daquan Yu

    J. Semicond.  2013, 34(4): 045004

    doi: 10.1088/1674-4926/34/4/045004

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    Two innovative de-embedding methods are proposed for extracting an electrical model for a through-silicon-via (TSV) pair consisting of a ground-signal (GS) structure. In addition, based on microwave network theory, a new solution scheme is developed for dealing with multiple solutions of the transfer matrix during the process of de-embedding. A unique solution is determined based on the amplitude and the phase characteristic of S parameters. In the first de-embedding method, a typical "π" type model of the TSV pair is developed, which illustrates the need to allow for frequency dependence in the equivalent TSV pair Spice model. This de-embedding method is shown to be effective for extracting the electrical properties of the TSVs. The feasibility of a second de-embedding method is also investigated.

  • A dual-path, current-sensing resistor-free boost LED driver with fast PWM dimming

    Minchao Zhou, Danzhu Lü, Lin Cheng, BillYang Liu, Zhiliang Hong

    J. Semicond.  2013, 34(4): 045005

    doi: 10.1088/1674-4926/34/4/045005

    Abstract Full Text PDF Get Citation

    A boost LED driver featuring a high PWM dimming ratio and optimized efficiency is presented. This LED driver, which has a low dropout voltage and is able to drive 3-7 LEDs in series with constant output current and fast PWM dimming, provides an alternative technique for brightness adjustment. A dual-path control scheme with automatic switching and state maintenance is proposed. Meanwhile, a cascode current mirror structure is applied with the output transistor multiplexed as an LED PWM dimming transistor. Implemented in 0.5 μm 25 V BCD process, the measurement results show that a voltage conversion range of 5 V input to 6-24 V output with constant output current is obtained. With automatically switching dual-path control and an optimized current mirror, the response time during PWM dimming is reduced to as low as 240 ns and the efficiency keeps above 89% over a wide PWM dimming ratio@250 mA output current.

  • Feed-through cancellation of a MEMS filter using the difference method and analysis of the induced notch

    Guowei Han, Chaowei Si, Jin Ning, Weiwei Zhong, Guosheng Sun, Yongmei Zhao, Fuhua Yang

    J. Semicond.  2013, 34(4): 045006

    doi: 10.1088/1674-4926/34/4/045006

    Abstract Full Text PDF Get Citation

    This paper presents and analyzes a notch observed in MEMS (micro electric mechanical system) filter characterization using the difference method. The difference method takes advantage of the cancellation of parasitic feed-through, which could potentially obscure the relatively small motional signal and lead to failure in characterization of the MEMS components. In this paper, typical clamped-clamped beam MEMS filters are fabricated and characterized with the difference method. Using the difference method a better performance is obtained but a notch is induced as a potential problem. Analysis is performed and reveals the mismatch of the two differential excitation signals in measurement circuit contributes to the notch. The relevant circuit design rule is also proposed to avoid the notch in the difference method.

  • A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration

    Yingying Chi, Dongmei Li

    J. Semicond.  2013, 34(4): 045007

    doi: 10.1088/1674-4926/34/4/045007

    Abstract Full Text PDF Get Citation

    A power efficient 96.1 dB-SFDR successive approximation register (SAR) analog-to-digital converter (ADC) with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18 μm CMOS. The charge redistribution (CR) design and an extra ΔΣ modulator for capacitance measurement are employed. With a 1.1 MS/s sampling rate, the ADC achieves 70.8 dB SNDR and the power consumption is 2.1 mW.

  • SRAM standby leakage decoupling analysis for different leakage reduction techniques

    Qing Dong, Yinyin Lin

    J. Semicond.  2013, 34(4): 045008

    doi: 10.1088/1674-4926/34/4/045008

    Abstract Full Text PDF Get Citation

    SRAM standby leakage reduction plays a pivotal role in minimizing the power consumption of application processors. Generally, four kinds of techniques are often utilized for SRAM standby leakage reduction:Vdd lowering (VDDL), Vss rising (VSSR), BL floating (BLF) and reversing body bias (RBB). In this paper, we comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage. It is disclosed that the performance of these techniques depends on the leakage composition of the SRAM cell and temperature. This has been verified on a 65 nm SRAM test macro.

  • C-band 6-bit phase shifter for a phase array antenna

    Xiaofeng Yang, Jiangyi Shi

    J. Semicond.  2013, 34(4): 045009

    doi: 10.1088/1674-4926/34/4/045009

    Abstract Full Text PDF Get Citation

    A C-band 6-bit digital phase shifter is presented. The phase shifter is based on the synthetic design of a high-pass/low-pass network and the all-pass network. The series scatter restrain method is also discussed. The phase shifter is fabricated in 0.25 μm GaAs PHEMT technology and developed for C-band phased arrays, and the relative phase shift varies from 0 to 360 in step of 5.625°. The phase shifter, with a chip size of 4×1.95 mm2, has achieved an insertion loss better than 6.4 dB, RMS phase error of less than 1.73°, and an input and output VSWR less than 1.6 at all conditions.

  • A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process

    Zhaonian Yang, Hongxia Liu, Shulong Wang

    J. Semicond.  2013, 34(4): 045010

    doi: 10.1088/1674-4926/34/4/045010

    Abstract Full Text PDF Get Citation

    An electrostatic discharge (ESD) detection circuit with a modified RC network for a 90-nm process clamp circuit is proposed. The leakage current is reduced to 4.6 nA at 25℃. Under the ESD event, it injects a 38.7 mA trigger current into the P-substrate to trigger SCR, and SCR can be turned on the discharge of the ESD energy. The capacitor area used is only 4.2 μm2. The simulation result shows that the proposed circuit can save power consumption and layout area when achieving the same trigger efficiency, compared with the previous circuits.

  • A low noise multi-channel readout IC for X-ray cargo inspection

    Xu Wang, Hongyan Yang, Ying Yuan, Wuchen Wu

    J. Semicond.  2013, 34(4): 045011

    doi: 10.1088/1674-4926/34/4/045011

    Abstract Full Text PDF Get Citation

    A low noise multi-channel readout integrated circuit (IC) which converts a detector current to analog voltage for X-ray cargo inspection is described. The readout IC provides 32 channels of a circuit having a maximum dynamic range of 15 bit and is comprised of integrator gain selection, timing generator, shift register chain, integrator array, sample/hold (S/H) stage amplifier etc. It was fabricated using 0.6 μm standard CMOS process, and occupies a die area of 2.7×13.9 mm2. It operates at 1 MHz, consumes 100 mW from a 5 V supply and 4.096 V as reference, and has a measured output noise of 85 μVrms on 63 pF of integrator gain capacitance and 440 pF of photodiode terminal capacitance so that steel plate penetration thickness can reach more than 400 mm.


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