Issue Browser

Volume 34, Issue 1, Jan 2013


  • Properties of a polaron in a quantum dot:a squeezed-state variational approach

    Jiwen Yin, Weiping Li, Yifu Yu

    J. Semicond.  2013, 34(1): 012001

    doi: 10.1088/1674-4926/34/1/012001

    Abstract Full Text PDF Get Citation

    The ground-state energy and the average number of virtual phonons around the electron in a parabolic quantum dot for the entire range of the electron-phonon coupling constant are obtained using the single-mode squeezed-state variational approach. The variational approach we applied is based on two successive canonical transformations and using a displaced-oscillator type unitary transformation to deal with the bilinear terms which are usually neglected. In order to study the relationship between the ground-state energy and the average number of virtual phonons around the electron of a polaron in a parabolic quantum dot with the electron-LO-phonon coupling constant and the confinement length, numerical calculations are carried out in the electron-LO-phonon strong-and weak-coupling regions.

  • Calculation of surface acoustic waves in a multilayered piezoelectric structure

    Zuwei Zhang, Zhiyu Wen, Jing Hu

    J. Semicond.  2013, 34(1): 012002

    doi: 10.1088/1674-4926/34/1/012002

    Abstract Full Text PDF Get Citation

    The propagation properties of the surface acoustic waves (SAWs) in a ZnO-SiO2-Si multilayered piezoelectric structure are calculated by using the recursive asymptotic method. The phase velocities and the electro-mechanical coupling coefficients for the Rayleigh wave and the Love wave in the different ZnO-SiO2-Si structures are calculated and analyzed. The Love mode wave is found to be predominantly generated since the c-axis of the ZnO film is generally perpendicular to the substrate. In order to prove the calculated results, a Love mode SAW device based on the ZnO-SiO2-Si multilayered structure is fabricated by micromachining, and its frequency responses are detected. The experimental results are found to be mainly consistent with the calculated ones, except for the slightly larger velocities induced by the residual stresses produced in the fabrication process of the films. The deviation of the experimental results from the calculated ones is reduced by thermal annealing.


  • Ultrasonic spray pyrolysis deposition of SnSe and SnSe2 using a single spray solution

    Jorge Sergio Narro-Rios, Manoj Ramachandran, Dalia Martínez-Escobar, Aarón Sánchez-Juárez

    J. Semicond.  2013, 34(1): 013001

    doi: 10.1088/1674-4926/34/1/013001

    Abstract Full Text PDF Get Citation

    Thin films of SnSe and SnSe2 have been deposited using the ultrasonic spray pyrolysis (USP) technique. To the best of our knowledge this is the first report of the deposition of SnSe and SnSe2 thin films using a single spray solution. The use of a single spray solution for obtaining both a p-type material, SnSe, and an n-type material, SnSe2, simplifies the deposition technique. The SnSe2 thin films have a bandgap of 1.1 eV and the SnSe thin films have a band gap of 0.9 eV. The Hall measurements were used to determine the resistivity of the thin films. The SnSe2 thin films show a resistivity of 36.73 Ω·cm and n-type conductivity while the SnSe thin films show a resistivity of 180 Ω·cm and p-type conductivity.

  • First-principles calculation on the concentration of intrinsic defects in 4H-SiC

    Ping Cheng, Yuming Zhang, Yimen Zhang

    J. Semicond.  2013, 34(1): 013002

    doi: 10.1088/1674-4926/34/1/013002

    Abstract Full Text PDF Get Citation

    Based on the first-principles pseudopotentials and the plane wave energy band method, the supercells of perfect crystal 4H-SiC and those with intrinsic defects VC, VSi, VC-C and VC-Si were calculated. Ignoring the atomic relaxations, the results show that the formation energy of intrinsic defects is ranked, from low to high, as VC, VC-C, VSi to VSi-Si at 0 K. The equilibrium concentration of each intrinsic defect can be deduced from the formation energy of each intrinsic defect. The concentration ranks, from high to low, as VC, VC-C, VSi, VSi-Si, which is in accordance with the ESR and PL results. The stabilizing process of metastable defects VSi converting to VC-C was explained by formation energy.

  • Cu doped AlSb polycrystalline thin films

    Lili Wu, Shuo Jin, Guanggen Zeng, Jingquan Zhang, Wei Li, Lianghuan Feng, Bing Li, Wenwu Wang

    J. Semicond.  2013, 34(1): 013003

    doi: 10.1088/1674-4926/34/1/013003

    Abstract Full Text PDF Get Citation

    Cu-doped AlSb polycrystalline films were grown on quartz glass by magnetron co-sputtering. The structural, morphological and electrical properties of the films were studied. The incorporation of copper atoms can result in the increase of lattice constants, and annealing is helpful to eliminate this deformation. Cu-doped AlSb films exhibit weak n-type conductivity. The results show that the doping effect has a close relationship with the annealing process, meaning that the position of Cu atom in AlSb polycrystalline films might influence the doping effect.


  • Effect of tunneling current on the noise characteristics of a 4H-SiC Read Avalanche diode

    Deepak K. Karan, Pranati Panda, G. N. Dash

    J. Semicond.  2013, 34(1): 014001

    doi: 10.1088/1674-4926/34/1/014001

    Abstract Full Text PDF Get Citation

    Noise characteristics of a Read Avalanche diode are analyzed by incorporating the tunneling mechanism of the electron into the avalanche mechanism. Analytical expressions are presented for the mean square noise voltage and noise measure in MITATT (mixed tunneling and avalanche transit time) mode operation. A wide band gap semiconductor (4H-SiC) based MITATT diode is considered to study the effect of tunneling on the noise characteristics and negative conductance. While exhibiting enough potential for 4H-SiC to be used as a terahertz source of power in the MITATT mode, our results record a noise measure of 35.18 dB at a frequency of 1.5 THz.

  • Analysis of the subthreshold characteristics of vertical tunneling field effect transistors

    Zhongfang Han, Guoping Ru, Gang Ruan

    J. Semicond.  2013, 34(1): 014002

    doi: 10.1088/1674-4926/34/1/014002

    Abstract Full Text PDF Get Citation

    Subthreshold characteristics of vertical tunneling field effect transistors (VTFETs) with an n+-pocket in the p+-source are studied by simulating the transfer characteristics with a commercial device simulator. Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations. Band diagram analysis shows that such a VTFET can be treated as a gate-controlled tunnel diode connected in series with a conventional n-channel metal-oxide-semiconductor FET. This VTFET can work either as a TFET or an n-MOSFET in the subthreshold region, depending on the turn-on sequence of these two components. To our knowledge, this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid. Our results indicate that the design of the n+ pocket is crucial for such a VTFET in order to achieve ultra-steep turn-on characteristics.

  • Capacitance and conductance dispersion in AlGaN/GaN heterostructure

    Dawei Yan, Fuxue Wang, Zhaomin Zhu, Jianmin Cheng, Xiaofeng Gu

    J. Semicond.  2013, 34(1): 014003

    doi: 10.1088/1674-4926/34/1/014003

    Abstract Full Text PDF Get Citation

    The dispersion mechanism in Al0.27Ga0.73N/GaN heterostructure was investigated using frequency-dependent capacitance and conductance measurements. It was found that the significant capacitance and conductance dispersion occurred primarily for measurement frequency beyond 100 kHz before the channel cutoff at the interface, suggesting that the vertical polarization electrical field under the gate metal should be closely related with the observed dispersive behavior. According to the Schottky-Read-Hall model, a traditional trapping mechanism cannot be used to explain our result. Instead, a piezoelectric polarization strain relaxation model was adopted to interpret the dispersion. By fitting the obtained capacitance data, the corresponding characteristic time and charge density were determined 10-8 s and 5.26×1012 cm-2 respectively, in good agreement with the conductance data and theoretical prediction.

  • Transconductance bimodal effect of PDSOI submicron H-gate MOSFETs

    Bo Mei, Jinshun Bi, Jianhui Bu, Zhengsheng Han

    J. Semicond.  2013, 34(1): 014004

    doi: 10.1088/1674-4926/34/1/014004

    Abstract Full Text PDF Get Citation

    A bimodal effect of transconductance was observed in narrow channel PDSOI sub-micron H-gate PMOSFETs, which was accompanied with the degeneration of device performance. This paper presents a study of the transconductance bimodal effect based on the manufacturing process and electrical properties of those devices. It is shown that this effect is caused by a diffusion of donor impurities from the N+ region of body contact to the P+ poly gate at the neck of the H-gate, which would change the work function differences of the polysilicon gate and substrate. This means that the threshold voltage of the device is different in the width direction, which means that there are parasitic transistors paralleled with the main transistor at the neck of the H-gate. The subsequent devices were fabricated with layout optimization, and it is demonstrated that the bimodal transconductance can be eliminated by mask modification with N+ implantation more than 0.2 μm away from a poly gate.

  • SPT+-IGBT characteristics and optimization

    Weili Chu, Yangjun Zhu, Jie Zhang, Aibin Hu

    J. Semicond.  2013, 34(1): 014005

    doi: 10.1088/1674-4926/34/1/014005

    Abstract Full Text PDF Get Citation

    A novel advanced soft punch through (SPT) IGBT signed as SPT+-IGBT is investigated. Static and dynamic characteristics are simulated based on the 1200 V device structure and adopted technology. Extensive research on the structure optimization of SPT+-IGBT is presented and discussed. Compared with the structure of conventional IGBT, SPT+-IGBT has a much lower collector-emitter saturation voltage and better switching characteristics. Therefore it is very suitable for applications blocking a voltage higher than 3000 V. In addition, due to the improvement of switching speed achieved by using a thinner chip, SPT+-IGBT is also very competitive in 1200 V and 1700 V applications.

  • Increasing substrate resistance to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS

    Chuan He, Lingli Jiang, Hang Fan, Bo Zhang

    J. Semicond.  2013, 34(1): 014006

    doi: 10.1088/1674-4926/34/1/014006

    Abstract Full Text PDF Get Citation

    With the impact of the non-uniform turn-on phenomenon, the ESD robustness of high-voltage multi-finger devices is limited. This paper describes the operational mechanism of a GG-nLDMOS device under ESD stress conditions and analyzes the reason that causes the non-uniform turn-on characteristics of a multi-finger GG-nLDMOS device. By means of increasing substrate resistance, an optimized device structure is proposed to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS. This approach has been successfully verified in a 0.35 μm 40 V BCD process. The TLP test results reveal that increasing the substrate resistance can effectively enhance the turn-on uniformity of the 40 V multi-finger GG-nLDMOS device and improve its ESD robustness.

  • A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

    Hongwei Pan, Siyang Liu, Weifeng Sun

    J. Semicond.  2013, 34(1): 014007

    doi: 10.1088/1674-4926/34/1/014007

    Abstract Full Text PDF Get Citation

    The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure, when used in power-rail ESD (electro-static discharge) clamp circuits. In order to eliminate latch-up risk, this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current. The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.

  • Influence of CuxS back contact on CdTe thin film solar cells

    Zhi Lei, Lianghuan Feng, Guanggen Zeng, Wei Li, Jingquan Zhang, Lili Wu, Wenwu Wang

    J. Semicond.  2013, 34(1): 014008

    doi: 10.1088/1674-4926/34/1/014008

    Abstract Full Text PDF Get Citation

    We present a detailed study on CuxS polycrystalline thin films prepared by chemical bath method and utilized as back contact material for CdTe solar cells. The characteristics of the films deposited on Si-substrate are studied by XRD. The results show that as-deposited CuxS thin film is in an amorphous phase while after annealing, samples are in polycrystalline phases with increasing temperature. The thickness of CuxS thin films has great impact on the performance of CdS/CdTe solar cells. When the thickness of the film is about 75 nm the performance of CdS/CdTe thin film solar cells is found to be the best. The energy conversion efficiency can be higher than 12.19%, the filling factor is higher than 68.82% and the open-circuit voltage is more than 820 mV.


  • A novel broadband power amplifier in SiGe HBT technology

    Wenyuan Li, Qian Zhang

    J. Semicond.  2013, 34(1): 015001

    doi: 10.1088/1674-4926/34/1/015001

    Abstract Full Text PDF Get Citation

    A novel broadband power amplifier fabricated in 0.13 μm SiGe HBT technology is realized. The pseudo-differential structure is proposed to avoid the influence of the bonding wire due to the AC virtual ground created at the common emitter node. A compensated matching technique is adopted in interstage matching to expand bandwidth. A multi-stage broadband matching technique is used in an input/output matching network to offer broadband impedance matching, which ensures maximum power transfer. An adaptive bias circuit could improve linearity and efficiency in wide output power level. With 2.5 V power supply, the measured results achieve 96% 3-dB bandwidth (517-1470 MHz), 27.2 dB power gain, 26.9 dBm maximum output power, 19.7 dBm output 1 dB compression point, and 26.7% power added efficiency.

  • A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability

    Bin Li, Xiangning Fan, Wei Li, Li Zhang, Zhigong Wang

    J. Semicond.  2013, 34(1): 015002

    doi: 10.1088/1674-4926/34/1/015002

    Abstract Full Text PDF Get Citation

    A fully integrated hybrid integer/fractional frequency synthesizer is presented. With a single multi-band voltage-controlled-oscillator (VCO), the frequency synthesizer can support GPS, Galileo, Compass and TD-SCDMA standards. Design is carefully performed to trade off power, die area and phase noise performance. By reconfiguring between the integer mode and fractional mode, different frequency resolution requirements and a constant loop bandwidth for each standard can be achieved simultaneously. Moreover, a long sequence length, reduced hardware complexity multi-stage-noise-shaping (MASH) Δ-Σ modulator is employed to reduce fractional spur in the fractional mode. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer occupies an active area of 1.48 mm2 and draws a current of 13.4-16.2 mA from a 1.8 V power supply. The measured phase noise is lower than-80 dBc/Hz at 100 kHz offset and-113 to-124 dBc/Hz at 1 MHz offset respectively, while the measured reference spur is-71 dBc in integer mode and the fractional spur is-65 dBc in fractional mode.

  • A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

    Kuan Bao, Xiangning Fan, Wei Li, Zhigong Wang

    J. Semicond.  2013, 34(1): 015003

    doi: 10.1088/1674-4926/34/1/015003

    Abstract Full Text PDF Get Citation

    This paper reports a wideband passive mixer for direct conversion multi-standard receivers. A brief comparison between current-commutating passive mixers and active mixers is presented. The effect of source and load impedance on the linearity of a mixer is analyzed. Specially, the impact of the input impedance of the transimpedance amplifier (TIA), which acts as the load impedance of a mixer, is investigated in detail. The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology. The circuit is inductorless and can operate over a broad frequency range. On wafer measurements show that, with radio frequency (RF) ranges from 700 MHz to 2.3 GHz, the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency (IF) bandwidth of 10 MHz. The measured ⅡP3 is 9 dBm and the measured double-sideband noise figure (NF) is 10.6 dB at 10 MHz output. The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.

  • A wideband 0.13 μm CMOS LC-VCO for IMT-advanced and UWB applications

    Xin Tang, Fengyi Huang, Xusheng Tang, Mingchi Shao

    J. Semicond.  2013, 34(1): 015004

    doi: 10.1088/1674-4926/34/1/015004

    Abstract Full Text PDF Get Citation

    This paper presents an LC voltage controlled oscillator (VCO) in a dual-band frequency synthesizer for IMT-advanced and UWB applications. The switched current source, cross-coupled pair and noise filtering technique are adopted in this VCO design to improve the performance of the phase noise, power consumption, voltage amplitude, and tuning range. In order to achieve a wide tuning range, a reconfigurable LC tank with 4 bits switch control is adopted in the core circuit design. The size of the entire chip with pad is 1.11×0.98 mm2. The test results show that the current dissipation of the VCO at UWB and IMT-Advanced band is 3 mA and 4.5 mA in a 1.2 V supply. The tuning range of the designed VCO is 3.86-5.28 GHz and 3.14-3.88 GHz. The phase-noise at 1 MHz frequency offset from a 3.5 GHz and 4.2 GHz carrier is-123 dBc/Hz and-119 dBc/Hz, respectively.

  • Design of a novel mixer with high gain and linearity improvement for DRM/DAB applications

    Yiqiang Wu, Zhigong Wang, Jian Xu, Jian Wang, Ouli Zhang, Lu Tang

    J. Semicond.  2013, 34(1): 015005

    doi: 10.1088/1674-4926/34/1/015005

    Abstract Full Text PDF Get Citation

    This paper focuses on a new design of a down-conversion mixer for a low-IF wideband receiver. Based on the folded structure and differential multiple gated transistor (DMGTR) technique, a novel quadrature mixer with a high conversion gain, a moderate linearity, and a moderate NF is proposed. The mixer is designed and implemented in a 0.18-μm CMOS process, and can operate in a frequency range from 150 kHz to 1.5 GHz. The circuit performance is confirmed by both simulation and measurement results. The measurement results exhibit a peak conversion gain of 13.35 dB, a high third order input referred intercept point of 14.85 dBm, and a moderate single side band noise figure of 10.67 dB. Moreover, the whole quadrature mixer core occupies a compact die area of 0.122 mm2. It consumes a current of 3.96 mA (excluding the output buffers) under a single supply voltage of 1.8 V.

  • Total ionizing dose effects on a radiation-induced BiMOS analog-to-digital converter

    Xue Wu, Wu Lu, Yiyuan Wang, Jialing Xu, Leqing Zhang, Jian Lu, Xin Yu, Xingyao Zhang, Tianle Hu

    J. Semicond.  2013, 34(1): 015006

    doi: 10.1088/1674-4926/34/1/015006

    Abstract Full Text PDF Get Citation

    The total dose effect of an AD678 with a BiMOS process is studied. We investigate the performance degradation of the device in different bias states and at several dose rates. The results show that an AD678 can endure 3 krad(Si) at low dose rate and 5 krad(Si) at a high dose rate for static bias. The sensitive parameters to the bias states also differ distinctly. We find that the degradation is more serious on static bias. The underlying mechanisms are discussed in detail.

  • Monolithic quasi-sliding-mode controller for SIDO buck converter with a self-adaptive free-wheeling current level

    Xiaobo Wu, Qing Liu, Menglian Zhao, Mingyang Chen

    J. Semicond.  2013, 34(1): 015007

    doi: 10.1088/1674-4926/34/1/015007

    Abstract Full Text PDF Get Citation

    An analog implementation of a novel fixed-frequency quasi-sliding-mode controller for single-inductor dual-output (SIDO) buck converter in pseudo-continuous conduction mode (PCCM) with a self-adaptive free-wheeling current level (SFCL) is presented. Both small and large signal variations around the operation point are considered to achieve better transient response so as to reduce the cross-regulation of this SIDO buck converter. Moreover, an internal integral loop is added to suppress the steady-state regulation error introduced by conventional PWM-based sliding mode controllers. Instead of keeping it as a constant value, the free-wheeling current level varies according to the load condition to maintain high power efficiency and less cross-regulation at the same time. To verify the feasibility of the proposed controller, an SIDO buck converter with two regulated output voltages, 1.8 V and 3.3 V, is designed and fabricated in HEJIAN 0.35 μm CMOS process. Simulation and experiment results show that the transient time of this SIDO buck converter drops to 10 μs while the cross-regulation is reduced to 0.057 mV/mA, when its first load changes from 50 to 100 mA.

  • A wideband frequency synthesizer with VCO and AFC co-design for fast calibration

    Liheng Lou, Lingling Sun, Haijun Gao, Haiting Zhan

    J. Semicond.  2013, 34(1): 015008

    doi: 10.1088/1674-4926/34/1/015008

    Abstract Full Text PDF Get Citation

    A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS process. It employs a wideband LC voltage-controlled oscillator (VCO) with optimized VCO gain (KVCO) and a sub-band step to improve automatic frequency calibration (AFC) efficiency at negligible expense of phase noise performance. An agile AFC is realized by direct mapping based on the division ratio, and optional redundant counting and comparing calibration is introduced accommodating PVT variations, which samples the reference clock using the prescaled VCO output as a discriminating clock. A charge pump with switched charging current is adopted to compensate for the loop bandwidth variation. Measurement results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 μs for redundant calibration. The frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz, with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.

  • A new LTPS TFT AC pixel circuit for an AMOLED

    Yongwen Zhang, Wenbin Chen

    J. Semicond.  2013, 34(1): 015009

    doi: 10.1088/1674-4926/34/1/015009

    Abstract Full Text PDF Get Citation

    This work presents a new voltage programmed pixel circuit for an active-matrix organic light-emitting diode (AMOLED) display. The proposed pixel circuit consists of six low temperature polycrystalline silicon thin-film transistors (LTPS TFTs), one storage capacitor, and one OLED, and is verified by simulation work using HSPICE software. Besides effectively compensating for the threshold voltage variation of the driving TFT and OLED, the proposed pixel circuit offers an AC driving mode for the OLED, which can suppress the degradation of the OLED. Moreover, a high contrast ratio can be achieved by the proposed pixel circuit since the OLED does not emit any light except for the emission period.

  • An 11-bit ENOB, accuracy-programmable, and non-calibrating time-mode SAR ADC

    Hua Fan, Xue Han, Qi Wei, Huazhong Yang

    J. Semicond.  2013, 34(1): 015010

    doi: 10.1088/1674-4926/34/1/015010

    Abstract Full Text PDF Get Citation

    A 10 or 12 bit programmable successive approximation register (SAR) ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented. Techniques for improving the accuracy of time-domain comparator are presented. The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC. Prototyped in a 0.18-μm, 6M1P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist signal-to-noise-plus-distortion ratio (SNDR) of 68 dB (11 ENOB), a spurious free dynamic range (SFDR) of 77.48 dB, while dissipating 558 μW from a 1.8-V supply. Its differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.2/-0.74 LSB and +1.27/-0.97 LSB, respectively.


Advanced Search >>


XML 地图 | Sitemap 地图