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Volume 33, Issue 9, Sep 2012

    SEMICONDUCTOR PHYSICS

  • Dielectric confinement on exciton binding energy and nonlinear optical properties in a strained Zn1-xinMgxinSe/Zn1-xoutMgxoutSe quantum well

    J. Abraham Hudson Mark, A. John Peter

    J. Semicond.  2012, 33(9): 092001

    doi: 10.1088/1674-4926/33/9/092001

    Abstract PDF Get Citation

    The band offsets for a Zn1-xinMgxinSe/Zn1-xoutMgxoutSe quantum well heterostructure are determined using the model solid theory. The heavy hole exciton binding energies are investigated with various Mg alloy contents. The effect of mismatch between the dielectric constants between the well and the barrier is taken into account. The dependence of the excitonic transition energies on the geometrical confinement and the Mg alloy is discussed. Non-linear optical properties are determined using the compact density matrix approach. The linear, third order non-linear optical absorption coefficient values and the refractive index changes of the exciton are calculated for different concentrations of magnesium. The results show that the occurred blue shifts of the resonant peak due to the Mg incorporation give the information about the variation of two energy levels in the quantum well width.

  • Chaotic dynamics dependence on doping density in weakly coupled GaAs/AlAs superlattices

    Yang Gui, Li Yuanhong, Zhang Fengying, Li Yuqi

    J. Semicond.  2012, 33(9): 092002

    doi: 10.1088/1674-4926/33/9/092002

    Abstract PDF Get Citation

    A discrete sequential tunneling model is used for studying the influence of the doping density on the dynamical behaviors in weakly coupled GaAs/AlAs superlattices. Driven by the DC bias, the system exhibits self-sustained current oscillations induced by the period motion of the unstable electric field domain, and an electrical hysteresis in the loop of current density voltage curve is deduced. It is found that the hysteresis range strongly depends on the doping density, and the width of the hysteresis loop increases with increasing the doping density. By adding an external driving ac voltage, more complicated nonlinear behaviors are observed including quasi-periodicity, period-3, and the route of an inverse period-doubling to chaos when the driving frequency changes.

  • A tunneling piezoresistive model for polysilicon

    Chuai Rongyan, Wang Jian, Wu Meile, Liu Xiaowei, Jin Xiaoshi, Yang Lijian

    J. Semicond.  2012, 33(9): 092003

    doi: 10.1088/1674-4926/33/9/092003

    Abstract PDF Get Citation

    Based on the trap model, the band structure and the conductive mechanism of polysilicon were analyzed, and then an equivalent circuit used to interpret the tunneling piezoresistive effect was proposed. Synthesizing the piezoresistive effect of the grain boundary region and grain neutral zone, a new piezoresistive model—a tunneling piezoresistive model is established. The results show that when the doping concentration is above 1020 cm-3, the piezoresistive coefficient of the grain boundary is higher than that of the neutral zone, and it increases with an increase in doping concentration. This reveals the intrinsic mechanism of an important experimental phenomena that the gauge factor of heavily doped polysilicon nano-films increases with an increase in doping concentration.

  • SEMICONDUCTOR MATERIALS

  • Effect of substrate temperature on the stability of transparent conducting cobalt doped ZnO thin films

    Said Benramache, Boubaker Benhaoua, Foued Chabane

    J. Semicond.  2012, 33(9): 093001

    doi: 10.1088/1674-4926/33/9/093001

    Abstract PDF Get Citation

    Transparent conducting Co doped ZnO thin films have been fabricated by Ultrasonic spray. The thin films were deposited at three different substrate temperatures of 300, 350 and 400 ℃. The obtained films had a hexagonal wurtzite structure with a strong (002) preferred orientation. The maximum crystallite size value of the film deposited at 350 ℃ is 55.46 nm. Spectrophotometer (UV-vis) of a Co doped ZnO film deposited at 350 ℃ shows an average transmittance of about 90%. The band gap energy increased from 3.351 to 3.362 eV when the substrate temperature increased from 300 to 350 ℃. The electrical conductivity of the films deposited at 300, 350 and 400 ℃ were 7.424, 7.547 and 6.743 (Ω·cm)-1 respectively. The maximum activation energy value of the films at 350 ℃ was 1.28 eV, indicating that the films exhibit a n-type semiconducting nature.

  • A nanostructured copper telluride thin film grown at room temperature by an electrodeposition method

    S. S. Dhasade, S. H. Han, V. J. Fulari

    J. Semicond.  2012, 33(9): 093002

    doi: 10.1088/1674-4926/33/9/093002

    Abstract PDF Get Citation

    Copper telluride onion flower like microstructures, constructed by quantum dots with various diameters, were obtained by a potentiostatic electrodeposition method at room temperature. The structural, optical, surface morphology, compositional analysis and Raman spectra properties of the deposited films have been studied using X-ray diffraction, optical absorption with scanning electron microscopy, EDAX, and Raman spectroscopy. The electrolyte concentration and deposition time can be used to control the diameter of the electrodeposited quantum dots to within a range of 50-55 nm. The films are found to be stoichiometric in composition. The optical constants such as the optical band gap energy and the optical absorption spectra show significant variation in their values with a change in deposition time. Upon deposition time the band gap energy increased from a value of 2.74 to 2.89 eV.

  • Effect of ZnO films on CdTe solar cells

    Liu Tingliang, He Xulin, Zhang Jingquan, Feng Lianghuan, Wu Lili, Li Wei, Zeng Guanggen, Li Bing

    J. Semicond.  2012, 33(9): 093003

    doi: 10.1088/1674-4926/33/9/093003

    Abstract PDF Get Citation

    The ZnO high resistivity transparent (HRT) layers were prepared by DC magnetron sputtering on the 1 mm borosilicate glass with 150 nm ITO coating. The structural, optical and electrical properties of the as-deposited films were investigated by XRD, UV/Vis spectroscopy and four-probe technology. The interface characters of the ITO/ZnO and ZnO/CdS systems were studied by ultraviolet photoelectron spectroscopy (UPS) and X-ray photoelectron spectroscopy (XPS) depth profiling tests. The results show that ZnO has good optical and electrical properties. The insertion of the ZnO films decreases the energy barrier between ITO and CdS films. The energy conversion efficiency and quantum efficiency were found to be 12.77% (8.9%) and > 90% (79%) with or (without) ZnO films of CdTe solar cells. Furthermore, the effect of thickness, mobility and carrier density of ZnO films on CdTe solar cells was analyzed by AMPD-1D.

  • Atomic layer deposition of an Al2O3 dielectric on ultrathin graphite by using electron beam irradiation

    Jiang Ran, Meng Lingguo, Zhang Xijian, Hyung-Suk Jung, Cheol Seong Hwang

    J. Semicond.  2012, 33(9): 093004

    doi: 10.1088/1674-4926/33/9/093004

    Abstract PDF Get Citation

    Atomic layer deposition of an Al2O3 dielectric on ultrathin graphite is studied in order to investigate the integration of a high k dielectric with graphite-based substrates. Electron beam irradiation on the graphite surface is followed by a standard atomic layer deposition of Al2O3. Improvement of the Al2O3 layer deposition morphology was observed when using this radiation exposure on graphite. This result may be attributed to the amorphous change of the graphite layers during electron beam irradiation.

  • Design of a three-layer hot-wall horizontal flow MOCVD reactor

    Gu Chengyan, Lee Chengming, Liu Xianglin

    J. Semicond.  2012, 33(9): 093005

    doi: 10.1088/1674-4926/33/9/093005

    Abstract PDF Get Citation

    A new three-layer hot-wall horizontal flow metal-organic chemical vapor deposition (MOCVD) reactor is proposed. When the susceptor is heated, the temperature of the wall over the susceptor also increases to the same temperature. Furthermore, the flowing speed of the top layer is also increased by up to four times that of the bottom layer. Both methods effectively decrease the convection and make most of the metal organic (MO) gas and the reactive gas distribute at the bottom surface of the reactor. By selecting appropriate shapes, sizes, nozzles array, and heating area of the walls, the source gases are kept in a laminar flow state. Results of the numeric simulation indicate that the nitrogen is a good carrier to reduce the diffusion among the precursors before arriving at the substrate, which leads to the reduction of pre-reaction. To get a good comparison with the conventional MOCVD horizontal reactor, the two-layer horizontal MOCVD reactor is also investigated. The results indicate that a two-layer reactor cannot control the gas flow effectively when its size and shape are the same as that of the three-layer reactor, so that the concentration distributions of the source gases in the susceptor surface are much more uniform in the new design than those in the conventional one.

  • SEMICONDUCTOR DEVICES

  • A fuzzy-logic-based approach to accurate modeling of a double gate MOSFETfor nanoelectronic circuit design

    F. Djeffal, A. Ferdi, M. Chahdi

    J. Semicond.  2012, 33(9): 094001

    doi: 10.1088/1674-4926/33/9/094001

    Abstract PDF Get Citation

    The double gate (DG) silicon MOSFET with an extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the drain current in the channel must be accurately determined under the application of drain and gate voltages. However, modeling the transport mechanism for the nanoscale structures requires the use of overkill methods and models in terms of their complexity and computation time (self-consistent, quantum computations, ...). Therefore, new methods and techniques are required to overcome these constraints. In this paper, a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs. The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic circuit design. The approach is general and thus is suitable for any type of nanoscale structure investigation problems in the nanotechnology industry.

  • Influence of thermal treatment temperatures on CdTe nanocrystal films and photoelectric properties of ITO/CdTe/Al

    Xu Wenqing, Qu Shengchun, Wang Kefan, Bi Yu, Liu Kong, Wang Zhanguo

    J. Semicond.  2012, 33(9): 094002

    doi: 10.1088/1674-4926/33/9/094002

    Abstract PDF Get Citation

    The influence of sintering temperatures on solution-processed cadmium telluride (CdTe) nanocrystal films is studied in order to maximize the performance of CdTe/Al Schottky nanocrystal solar cells. The best overall performance of 2.67% efficiency at air mass 1.5 was achieved from devices with CdTe films sintered at 350 ℃ X-ray diffraction, scanning electron microscopy and UV-vis absorption measurements show that the CdTe nanocrystal grains began to grow remarkably well when sintering temperatures increased to 350 ℃. By analyzing the current-voltage characteristics, we find that the short-circuit current densities of devices increase with sintering temperatures ranging from 200 to 400 ℃, but, the over-sintered (450 ℃) treatment induces the shunting of devices.

  • Turn-on and turn-off voltages of an avalanche p-n junction

    Zhang Guoqing, Han Dejun, Zhu Changjun, Zhai Xuejun

    J. Semicond.  2012, 33(9): 094003

    doi: 10.1088/1674-4926/33/9/094003

    Abstract PDF Get Citation

    Characteristics of the turn-on and turn-off voltage of avalanche p-n junctions were demonstrated and studied. As opposed to existing reports, the differences between the turn-on and turn-off voltage cannot be neglected when the size of the p-n junction is in the order of microns. The difference increases inversely with the area of a junction, exerting significant influences on characterizing some parameters of devices composed of small avalanche junctions. Theoretical analyses show that the mechanism for the difference lies in the increase effect of the threshold multiplication factor at the turn-on voltage of a junction when the area of a junction decreases. Moreover, the "breakdown voltage" in the formula of the avalanche asymptotic current is, in essence, the avalanche turn-off voltage, and consequently, the traditional expression of the avalanche asymptotic current and the gain of a Geiger mode avalanche photodiode were modified.

  • Effect of varying layouts on the gate temperature for multi-finger AlGaN/GaN HEMTs

    Wang Jianhui, Wang Xinhua, Pang Lei, Chen Xiaojuan, Jin Zhi, Liu Xinyu

    J. Semicond.  2012, 33(9): 094004

    doi: 10.1088/1674-4926/33/9/094004

    Abstract PDF Get Citation

    The impacts of varying layout geometries on the channel temperature of multi-finger AlGaN/GaN HEMTs are investigated by three-dimensional (3-D) thermal simulations. Micro-Raman thermography is selected to obtain a detailed and accurate temperature distribution of the sample for the verification of the 3-D thermal models. Thermal boundary resistance (TBR) plays an important role in the temperature distribution and is taken into account in the thermal model in order to improve the accuracy of the simulated results. The influence from the number of fingers, finger width and gate pitch on the gate temperature are systematically analysed using 3-D thermal simulations with validated model parameters. Furthermore, a robust method that could efficiently reduce the thermal crosstalk of multi-finger AlGaN/GaN HEMTs is proposed to optimize the thermal design of the device.

  • A strained Si-channel NMOSFET with low field mobility enhancement of about 140% using a SiGe virtual substrate

    Cui Wei, Tang Zhaohuan, Tan Kaizhou, Zhang Jing, Zhong Yi, Hu Huiyong, Xu Shiliu, Li Ping, Hu Gangyi

    J. Semicond.  2012, 33(9): 094005

    doi: 10.1088/1674-4926/33/9/094005

    Abstract PDF Get Citation

    A fully standard CMOS integrated strained Si-channel NMOSFET has been demonstrated. By adjusting the thickness of graded SiGe, modifying the channel doping concentration, changing the Ge fraction of the relaxed SiGe layer and forming a p-well by multiple implantation technology, a surface strained Si-channel NMOSFET was fabricated, of which the low field mobility was enhanced by 140%, compared with the bulk-Si control device. Strained NMOSFET and PMOSFET were used to fabricate a strained CMOS inverter based on a SiGe virtual substrate. Test results indicated that the strained CMOS converter had a drain leakage current much lower than the Si devices, and the device exhibited wonderful on/off-state voltage transmission characteristics.

  • A neutron radiation-hardened superluminescent diode

    Jiao Jian, Tan Manqing, Zhao Miao, Chang Jinlong

    J. Semicond.  2012, 33(9): 094006

    doi: 10.1088/1674-4926/33/9/094006

    Abstract PDF Get Citation

    We present a novel superluminescent diode (SLD) with high optical performances for hardened neutron irradiation. The degradation of the light output from the SLDs is caused by a reduction of the minority carrier lifetime resulting from displacement damage after high-energy neutron irradiation. The SLDs with a higher pre-irradiation light output will be less sensitive to radiation. We have selected an InGaAsP/InP multi-quantum well (MQW) as the active region structure for its performance, its high optical gain and minute active region. Graded-index separate-confinement-heterostructure (GRIN-SCH) has been applied for the waveguide structure. A specific absorbing region and anti-reflective coatings have been designed and optimized. Moreover, the radiation test results indicate that the SLD with an InGaAsP/InP MQW structure has better neutron hardening ability than the SLD with DH structures after a 6 × 1013-1 × 1014 n/cm2 1 MeV neutron irradiation.

  • Fabrication of high-voltage light emitting diodes with a deep isolation groove structure

    Ding Yan, Guo Weiling, Zhu Yanxu, Liu Ying, Liu Jianpeng, Yan Weiwei

    J. Semicond.  2012, 33(9): 094007

    doi: 10.1088/1674-4926/33/9/094007

    Abstract PDF Get Citation

    In order to connect several independent LEDs in series, inductively coupled plasma (ICP) deep etching of GaN is required for isolation. The GaN-based high-voltage (HV) LEDs with a 5 μm deep isolation groove and an acceptable mesa sidewall angle of 79.2° are fabricated and presented. The surface morphology and construction profile of the etched groove are characterized by laser microscopy and scanning electron microscopy. After contact metal formation and annealing, the electrical properties are evaluated by I-V characteristics. The trend of the I-V curve has good accordance with conventional LEDs. The contact resistance of HV LEDs is also tested and was reduced by 4.6 Ω compared to conventional LEDs, while the output power increased by 5 W. The results show that this technique can be applied to practical fabrication.

  • Improving poor fill factors for solar cells via light-induced plating

    Xing Zhao, Jia Rui, Ding Wuchang, Meng Yanlong, Jin Zhi, Liu Xinyu

    J. Semicond.  2012, 33(9): 094008

    doi: 10.1088/1674-4926/33/9/094008

    Abstract PDF Get Citation

    Silicon solar cells are prepared following the conventional fabrication processes, except for the metallization firing process. The cells are divided into two groups with higher and lower fill factors, respectively. After light-induced plating (LIP), the fill factors of the solar cells in both groups with different initial values reach the same level. Scanning electron microscope (SEM) images are taken under the bulk silver electrodes, which prove that the improvement for cells with a poor factor after LIP should benefit from sufficient exploitation of the high density silver crystals formed during the firing process. Moreover, the application of LIP to cells with poor electrode contact performance, such as nanowire cells and radial junction solar cells, is proposed.

  • Design and process test of a novel MOEMS accelerometer based on Raman-Nath diffraction

    Zhang Zuwei, Wen Zhiyu, Shang Zhengguo, Li Dongling, Hu Jing

    J. Semicond.  2012, 33(9): 094009

    doi: 10.1088/1674-4926/33/9/094009

    Abstract PDF Get Citation

    A novel micro-opto-electro-mechanical system (MOEMS) accelerometer based on Raman-Nath diffraction is presented. It mainly consists of an FPW delay line oscillator and optical strip waveguides. The fundamental theories and principles of the device are introduced briefly. A flexural plate-wave delay-line oscillator is designed to work as an acousto-optic (AO) shifter, which has a Klein-Cook parameter of 0.38. Single-mode optical strip waveguides of 2 μm in width and thicknesses of 0.6 μm are designed by using the effective index method for light transmission. The E00y mode waveguide polarizers are designed to ensure the consistency of the light polarization in the waveguides. The fabrication process, based on (100) oriented, 450-μm-thick silicon wafers is proposed in detail, and some difficulties in the process are discussed carefully. At last, a series of process tests are undertaken to solve the proposed problems. The results indicate that the proposed design and fabrication process of the device is dependable and realizable.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • A novel low ripple charge pump with a 2X/1.5X booster for PCM

    Fu Cong, Song Zhitang, Chen Houpeng, Cai Daolin, Wang Qian, Hong Xiao, Ding Sheng, Li Xi

    J. Semicond.  2012, 33(9): 095001

    doi: 10.1088/1674-4926/33/9/095001

    Abstract PDF Get Citation

    A low ripple switched capacitor charge pump applicable to phase change memory (PCM) is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo-Vin during the charge phase (Vo is the prospective output voltage). In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.

  • High efficiency class-I audio power amplifier using a single adaptive supply

    Peng Zhenfei, Yang Shanshan, Feng Yong, Liu Yang, Hong Zhiliang

    J. Semicond.  2012, 33(9): 095002

    doi: 10.1088/1674-4926/33/9/095002

    Abstract PDF Get Citation

    A high efficiency class-I linear audio power amplifier (PA) with an adaptive supply is presented. Its efficiency is improved by a dynamic supply to reduce the power transistors' voltage drop. A gain compression technique is adopted to make the amplifier accommodate a single positive supply. Circuit complicity and chip area are reduced because no charge pump is necessary for the negative supply. A common shared mode voltage and a symmetric layout pattern are used to minimize the non-linearity. A peak efficiency of 80% is reached at peak output power. The measured THD+N before and after the supply switching point are 0.01% and 0.05%, respectively. The maximum output power is 410 mW for an 8 Ω speaker load. Unlike switching amplifiers, the class-I amplifier operates as a linear amplifier and hence has a low EMI. The advantage of a high efficiency and low EMI makes the class-I amplifier suitable for portable and RF sensitive applications.

  • A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

    Guo Rui, Zhang Haiying

    J. Semicond.  2012, 33(9): 095003

    doi: 10.1088/1674-4926/33/9/095003

    Abstract PDF Get Citation

    A fully integrated multi-mode multi-band directed-conversion radio frequency (RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented. The front-end employs direct-conversion design, and consists of two differential tunable low noise amplifiers (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers. The two independent tunable LNAs are used to cover all the four frequency bands, achieving sufficient low noise and high gain performance with low power consumption. Switched capacitor arrays perform a resonant frequency point calibration for the LNAs. The two LNAs are combined at the driver stage of the mixer, which employs a folded double balanced Gilbert structure, and utilizes PMOS transistors as local oscillator (LO) switches to reduce flicker noise. The front-end has three gain modes to obtain a higher dynamic range. Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface (SPI) module. The front-end is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm2. The measured double-sideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.

  • A low power 14 bit 51.2 kS/s double-sampling extended counting ADC with a class-AB OTA

    Chen Honglei, Wu Dong, Shen Yanzhao, Xu Jun

    J. Semicond.  2012, 33(9): 095004

    doi: 10.1088/1674-4926/33/9/095004

    Abstract PDF Get Citation

    A 14 bit 51.2 kS/s extended counting analog to digital converter (EC-ADC) is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilinear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier (OTA) is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 pJ/step.

  • A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

    Qiao Ning, Zhang Guoquan, Yang Bo, Liu Zhongli, Yu Fang

    J. Semicond.  2012, 33(9): 095005

    doi: 10.1088/1674-4926/33/9/095005

    Abstract PDF Get Citation

    A 10-bit 50-MS/s reference-free low power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC (CDAC) is implemented to cancel the offset of the latch-type sense amplifier (SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit (FOM) of 61.1 fJ/conversion-step.

  • A novel high performance ESD power clamp circuit with a small area

    Yang Zhaonian, Liu Hongxia, Li Li, Zhuo Qingqing

    J. Semicond.  2012, 33(9): 095006

    doi: 10.1088/1674-4926/33/9/095006

    Abstract PDF Get Citation

    A MOSFET-based electrostatic discharge (ESD) power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. The special structure overcomes other shortcomings in this clamp circuit. Under fast power-up events, the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events, the special structure can keep the clamp MOSFET thoroughly off. Under a falsely triggered event, the special structure can turn off the clamp MOSFET in a short time. The clamp circuit can also reject the power supply noise effectively. Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up, maintains a 1.2 μs delay time and a 2.14 μs turn-off time, and reduces to about 70% of the RC time constant. It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.

  • A low-power low-voltage slew-rate enhancement circuit for two-stage operational amplifiers

    Shu Chen, Xu Jun, Ye Fan, Ren Junyan

    J. Semicond.  2012, 33(9): 095007

    doi: 10.1088/1674-4926/33/9/095007

    Abstract PDF Get Citation

    A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers. The enhancer utilizes the class-AB input stage to improve current efficiency, while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier. During the slewing period, the enhancer detects input differential voltage of the amplifier, and produces external enhancement currents for the amplifier, driving load capacitors to charge/discharge faster. Simulation results show that, for a large input step, the enhancer reduces settling time by nearly 50%. When the circuit is employed in a sample-and-hold circuit, it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB. The proposed circuit is very suitable to operate under a low voltage (1.2 V or below) with a standby current of 200 μA.

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