Recently there has been a rapid domestic development in group III nitride semiconductor electronic materials and devices. This paper reviews the important progress in GaN-based wide bandgap microelectronic materials and devices in the Key Program of the National Natural Science Foundation of China, which focuses on the research of the fundamental physical mechanisms of group III nitride semiconductor electronic materials and devices with the aim to enhance the crystal quality and electric performance of GaN-based electronic materials, develop new GaN heterostructures, and eventually achieve high performance GaN microwave power devices. Some remarkable progresses achieved in the program will be introduced, including those in GaN high electron mobility transistors (HEMTs) and metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with novel high-k gate insulators, and material growth, defect analysis and material properties of InAlN/GaN heterostructures and HEMT fabrication, and quantum transport and spintronic properties of GaN-based heterostructures, and high-electric-field electron transport properties of GaN material and GaN Gunn devices used in terahertz sources.
J. Semicond. 2012, 33(8): 081001
doi: 10.1088/1674-4926/33/8/081001Hao Yue, Zhang Jinfeng, Shen Bo, Liu Xinyu. Progress in Group III nitride semiconductor electronic devices[J]. 威尼斯人棋牌, 2012, 33(8): 081001. doi: 10.1088/1674-4926/33/8/081001.
Hao Y, Zhang J F, Shen B, Liu X Y. Progress in Group III nitride semiconductor electronic devices[J]. J. Semicond., 2012, 33(8): 081001. doi: 10.1088/1674-4926/33/8/081001.Export: BibTex EndNote
Structural, electronic, magnetic and optical properties of neodymium chalcogenides using LSDA+U method
J. Semicond. 2012, 33(8): 082001
doi: 10.1088/1674-4926/33/8/082001A Shankar, D P Rai, Sandeep, R K Thapa. Structural, electronic, magnetic and optical properties of neodymium chalcogenides using LSDA+U method[J]. 威尼斯人棋牌, 2012, 33(8): 082001. doi: 10.1088/1674-4926/33/8/082001.
A Shankar, D P Rai, Sandeep, R K Thapa. Structural, electronic, magnetic and optical properties of neodymium chalcogenides using LSDA+U method[J]. J. Semicond., 2012, 33(8): 082001. doi:?10.1088/1674-4926/33/8/082001.Export: BibTex EndNote
We have studied the electronic, magnetic and optical properties of neodymium chalcogenides by performing LSDA+U and full potential linearized augmented plane wave (FP-LAPW) method. The electronic structure calculation shows that the electronic states in Nd-chalcogenides were mainly contributed by Nd-4f electrons near Fermi energy and 3p, 4p and 5p state electrons of X (S, Se and Te), respectively. We have also studied the absorption of light via the imaginary parts of the dielectric function of Nd-chalcogenides.
J. Semicond. 2012, 33(8): 082002
doi: 10.1088/1674-4926/33/8/082002A. M. Saleh, S. M. Hraibat, R. M-L. Kitaneh, M. M. Abu-Samreh, S. M. Musameh. Dielectric response and electric properties of organic semiconducting phthalocyanine thin films[J]. 威尼斯人棋牌, 2012, 33(8): 082002. doi: 10.1088/1674-4926/33/8/082002.
A M Saleh, S M Hraibat, R M L Kitaneh, M M Abu-Samreh, S M Musameh. Dielectric response and electric properties of organic semiconducting phthalocyanine thin films[J]. J. Semicond., 2012, 33(8): 082002. doi:?10.1088/1674-4926/33/8/082002.Export: BibTex EndNote
The dielectric function of some phthalocyanine compounds (ZnPc, H2Pc, CuPc, and FePc) were investigated by analyzing the measured capacitance and loss tangent data. The real part of the dielectric constant, ε1, varies strongly with frequency and temperature. The frequency dependence was expressed as: ε1 = Aωn, where the index, n, assumes negative values (n < 0). In addition, the imaginary part of the dielectric constant, ε2, is also frequency and temperature dependent. Data analysis confirmed that ε2 = Bωm with values of m less than zero. At low frequencies and all temperatures, a strong dependence is observed, while at higher frequencies, a moderate dependence is obvious especially for the Au-electrode sample. Qualitatively, the type of electrode material had little effect on the behavior of the dielectric constant but did affect its value. Analysis of the AC conductivity dependence on frequency at different temperatures indicated that the correlated barrier hopping (CBH) model is the most suitable mechanism for the AC conduction behavior. Maximum barrier height, W, has been estimated for ZnPc with different electrode materials (Au and Al), and had values between 0.10 and 0.9 eV. For both electrode types, the maximum barrier height has strong frequency dependence at high frequency and low temperatures. The relaxation time, τ, for ZnPc and FePc films increases with decreasing frequency. The activation energy was derived from the slopes of τ versus 1/T curves. At low temperatures, an activation energy value of about 0.01 eV and 0.04 eV was estimated for ZnPc and FePc, respectively. The low values of activation energy suggest that the hopping of charge carriers between localized states is the dominant mechanism.
J. Semicond. 2012, 33(8): 083001
doi: 10.1088/1674-4926/33/8/083001Shadia. J. Ikhmayies, Riyad N Ahmad-Bitar. Using I-V characteristics to investigate selected contacts for SnO2:F thin films[J]. 威尼斯人棋牌, 2012, 33(8): 083001. doi: 10.1088/1674-4926/33/8/083001.
S J Ikhmayies, R N Ahmad-Bitar. Using I-V characteristics to investigate selected contacts for SnO2:F thin films[J]. J. Semicond., 2012, 33(8): 083001. doi:?10.1088/1674-4926/33/8/083001.Export: BibTex EndNote
Fluorine doped tin oxide (SnO2:F) thin films were prepared on glass substrates by the spray pyrolysis (SP) technique at different substrate temperatures between 380-480 ℃. The microstructure of the films was explored using scanning electron microscope observations. An investigation of selected contacts for the films was performed through the analysis of the I-V measurements which were taken in the dark at room temperature. Indium, aluminum and silver were selected as contacts where two strips of each metal were vacuum-evaporated on the surface of the film. The resistivity of the films was estimated from the linear I-V plots. It was found that the smallest resistivity was obtained using silver contacts, while the largest resistivity was obtained by using indium contacts. This is because silver diffuses in the film and participates in doping, while aluminum and indium cause compensation effects when they diffuse in the film. The best linear fit parameters are those of films with aluminum contacts, and the worst ones are those of films with indium contacts. Annealing was found to improve the electrical properties of the films, especially those deposited at a low substrate temperature. This is because it is expected to encourage crystal growth and to reduce the contact potential which leads to the formation of an alloy. Annealed films are more stable than un-annealed ones.
J. Semicond. 2012, 33(8): 083002
doi: 10.1088/1674-4926/33/8/083002Jia Baoshan, Wang Yunhua, Zhou Lu, Bai Duanyuan, Qiao Zhongliang, Gao Xin, Bo Baoxue. Influence of sputtering pressure on optical constants of a-GaAs1-xNx thin films[J]. 威尼斯人棋牌, 2012, 33(8): 083002. doi: 10.1088/1674-4926/33/8/083002.
Jia B S, Wang Y H, Zhou L, Bai D Y, Qiao Z L, Gao X, Bo B X. Influence of sputtering pressure on optical constants of a-GaAs1-xNx thin films[J]. J. Semicond., 2012, 33(8): 083002. doi: 10.1088/1674-4926/33/8/083002.Export: BibTex EndNote
Amorphous GaAs1-xNx (a-GaAs1-xNx) thin films have been deposited at room temperature by a reactive magnetron sputtering technique on glass substrates with different sputtering pressures. The thickness, nitrogen content, carrier concentration and transmittance of the as-deposited films were determined experimentally. The influence of sputtering pressure on the optical band gap, refractive index and dispersion parameters (Eo, Ed) has been investigated. An analysis of the absorption coefficient revealed a direct optical transition characterizing the as-deposited films. The refractive index dispersions of the as-deposited a-GaAs1-xNx films fitted well to the Cauchy dispersion relation and the Wemple model.
J. Semicond. 2012, 33(8): 083003
doi: 10.1088/1674-4926/33/8/083003Ge Liang, Hu Cheng, Zhu Zhiwei, Zhang Wei, Wu Dongping, Zhang Shili. Influence of surface preparation on atomic layer deposition of Pt films[J]. 威尼斯人棋牌, 2012, 33(8): 083003. doi: 10.1088/1674-4926/33/8/083003.
Ge L, Hu C, Zhu Z W, Zhang W, Wu D P, Zhang S L. Influence of surface preparation on atomic layer deposition of Pt films[J]. J. Semicond., 2012, 33(8): 083003. doi: 10.1088/1674-4926/33/8/083003.Export: BibTex EndNote
We report Pt deposition on a Si substrate by means of atomic layer deposition (ALD) using (methylcyclopentadienyl) trimethylplatinum (CH3C5H4Pt(CH3)3) and O2. Silicon substrates with both HF-last and oxide-last surface treatments are employed to investigate the influence of surface preparation on Pt-ALD. A significantly longer incubation time and less homogeneity are observed for Pt growth on the HF-last substrate compared to the oxide-last substrate. An interfacial oxide layer at the Pt-Si interface is found inevitable even with HF treatment of the Si substrate immediately prior to ALD processing. A plausible explanation to the observed difference of Pt-ALD is discussed.
J. Semicond. 2012, 33(8): 084001
doi: 10.1088/1674-4926/33/8/084001R K Parida, N C Agrawala, G N Dash, A K Panda. Characteristics of a GaN-based Gunn diode for THz signal generation[J]. 威尼斯人棋牌, 2012, 33(8): 084001. doi: 10.1088/1674-4926/33/8/084001.
R K Parida, N C Agrawala, G N Dash, A K Panda. Characteristics of a GaN-based Gunn diode for THz signal generation[J]. J. Semicond., 2012, 33(8): 084001. doi:?10.1088/1674-4926/33/8/084001.Export: BibTex EndNote
A generalized large-signal computer simulation program for a Gunn oscillator has been developed. The properties of a Gunn diode oscillator based on the widely explored GaN, are investigated using the developed program. The results show some interesting properties in GaN Gunn diodes which are not seen in GaAs and InP diodes. An output power of 1400 kW/cm2 is achieved from the GaN Gunn diode, as compared to 4.9 kW/cm2 from a GaAs diode.
J. Semicond. 2012, 33(8): 084002
doi: 10.1088/1674-4926/33/8/084002Wang Gang, Li Wei, Li Ping, Li Zuxiong, Fan Xue, Jiang Jing. A novel antifuse structure based on amorphous bismuth zinc niobate thin films[J]. 威尼斯人棋牌, 2012, 33(8): 084002. doi: 10.1088/1674-4926/33/8/084002.
Wang G, Li W, Li P, Li Z X, Fan X, Jiang J. A novel antifuse structure based on amorphous bismuth zinc niobate thin films[J]. J. Semicond., 2012, 33(8): 084002. doi: 10.1088/1674-4926/33/8/084002.Export: BibTex EndNote
A novel antifuse structure with amorphous bismuth zinc niobate (a-BZN) dielectrics was proposed. The characteristics of the a-BZN antifuse were investigated. Programming direction of up to down was chosen to rupture the a-BZN antifuse. The breakdown voltage of the a-BZN antifuse was obtained at a magnitude of 6.56 V. A large off-state resistance of more than 1 GΩ for the a-BZN antifuse was demonstrated. The surface micrograph of the ruptured a-BZN antifuses was illustrated. Programming characteristics with the programming time of 0.46 ms and on-state properties with the average resistance value of 26.1 Ω of the a-BZN antifuse were exhibited. The difference of characteristics of the a-BZN antifuse from that of a cubic pyrochlore bismuth zinc niobate (cp-BZN) antifuse and gate oxide antifuse was compared and analyzed.
J. Semicond. 2012, 33(8): 084003
doi: 10.1088/1674-4926/33/8/084003Dai Zhenqing, Chen Changxin, Zhang Yaozhong, Wei Liangming, Zhang Jing, Xu Dong, Zhang Yafei. ZnO nanowire network transistors based on a self-assembly method[J]. 威尼斯人棋牌, 2012, 33(8): 084003. doi: 10.1088/1674-4926/33/8/084003.
Dai Z Q, Chen C X, Zhang Y Z, Wei L M, Zhang J, Xu D, Zhang Y F. ZnO nanowire network transistors based on a self-assembly method[J]. J. Semicond., 2012, 33(8): 084003. doi: 10.1088/1674-4926/33/8/084003.Export: BibTex EndNote
Dense, uniform ZnO nanowire (NW) networks are prepared by using a simple and sufficient self-assembly method. In this method, ZnO NWs are modified with aminopropyltriethoxysilane (APTES) to form positively charged amine-terminated surfaces. The modified ZnO NWs are adsorbed on negatively charged SiO2/Si substrates to form ZnO NW networks by the electrostatic interaction in an aqueous solution. Field-effect transistors (FETs) are fabricated and studied based on the ZnO NW networks. For a typical device with an NW density of 2.8 μm-2, it exhibits a current on/off ratio of 2.4 × 105, a transconductance of 336 nS, and a field-effect mobility of 27.4 cm2/(V·s).
J. Semicond. 2012, 33(8): 084004
doi: 10.1088/1674-4926/33/8/084004Cui Ning, Liang Renrong, Wang Jing, Zhou Wei, Xu Jun. A PNPN tunnel field-effect transistor with high-k gate and low-k fringe dielectrics[J]. 威尼斯人棋牌, 2012, 33(8): 084004. doi: 10.1088/1674-4926/33/8/084004.
Cui N, Liang R R, Wang J, Zhou W, Xu J. A PNPN tunnel field-effect transistor with high-k gate and low-k fringe dielectrics[J]. J. Semicond., 2012, 33(8): 084004. doi: 10.1088/1674-4926/33/8/084004.Export: BibTex EndNote
A PNPN tunnel field effect transistor (TFET) with a high-k gate dielectric and a low-k fringe dielectric is introduced. The effects of the gate and fringe electric fields on the TFET's performance were investigated through two-dimensional simulations. The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel, while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability. The TFET device with the proposed structure has good switching characteristics, enhanced on-state current, and high process tolerance. It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.
J. Semicond. 2012, 33(8): 084005
doi: 10.1088/1674-4926/33/8/084005Huang Haiyun, Wang Dejun, Li Wenbo, Xu Yue, Qin Huibin, Hu Yongcai. A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices[J]. 威尼斯人棋牌, 2012, 33(8): 084005. doi: 10.1088/1674-4926/33/8/084005.
Huang H Y, Wang D J, Li W B, Xu Y, Qin H B, Hu Y C. A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices[J]. J. Semicond., 2012, 33(8): 084005. doi: 10.1088/1674-4926/33/8/084005.Export: BibTex EndNote
A simplified compact model for a miniaturized cross-shaped CMOS integrated Hall device is presented. The model has a simple circuit structure, only consisting of a passive network with eight non-linear resistors and four current-controlled voltage sources. It completely considers the following effects: non-linear conductivity, geometry dependence of sensitivity, temperature drift, lateral diffusion, and junction field effect. The model has been implemented in Verilog-A hardware description language and was successfully performed in a Cadence Spectre simulator. The simulation results are in good accordance with the classic experimental results reported in the literature.
J. Semicond. 2012, 33(8): 084006
doi: 10.1088/1674-4926/33/8/084006Zhang Junyu, Wang Yong, Liu Jing, Zhang Manhong, Xu Zhongguang, Huo Zongliang, Liu Ming. A novel 2 T P-channel nano-crystal memory for low power/high speed embedded NVM applications[J]. 威尼斯人棋牌, 2012, 33(8): 084006. doi: 10.1088/1674-4926/33/8/084006.
Zhang J Y, Wang Y, Liu J, Zhang M H, Xu Z G, Huo Z L, Liu M. A novel 2 T P-channel nano-crystal memory for low power/high speed embedded NVM applications[J]. J. Semicond., 2012, 33(8): 084006. doi: 10.1088/1674-4926/33/8/084006.Export: BibTex EndNote
We introduce a novel 2 T P-channel nano-crystal memory structure for low power and high speed embedded non-volatile memory (NVM) applications. By using the band-to-band tunneling-induced hot-electron (BTBTIHE) injection scheme, both high-speed and low power programming can be achieved at the same time. Due to the use of a select transistor, the "erased states" can be set to below 0 V, so that the periphery HV circuit (high-voltage generating and management) and read-out circuit can be simplified. Good memory cell performance has also been achieved, including a fast program/erase (P/E) speed (a 1.15 V memory window under 10 μs program pulse), an excellent data retention (only 20% charge loss for 10 years). The data shows that the device has strong potential for future embedded NVM applications.
J. Semicond. 2012, 33(8): 084007
doi: 10.1088/1674-4926/33/8/084007Liu Jun, Zhong Lin, Wang Huang, Wen Jincai, Sun Lingling, Yu Zhiping, Marissa Condon. Double-π fully scalable model for on-chip spiral inductors[J]. 威尼斯人棋牌, 2012, 33(8): 084007. doi: 10.1088/1674-4926/33/8/084007.
Liu J, Zhong L, Wang H, Wen J C, Sun L L, Yu Z P, M Condon. Double-π fully scalable model for on-chip spiral inductors[J]. J. Semicond., 2012, 33(8): 084007. doi:?10.1088/1674-4926/33/8/084007.Export: BibTex EndNote
A novel double-π equivalent circuit model for on-chip spiral inductors is presented. A hierarchical structure, similar to that of MOS models is introduced. This enables a strict partition of the geometry scaling in the global model and the model equations in the local model. The major parasitic effects, including the skin effect, the proximity effect, the inductive and capacitive loss in the substrate, and the distributed effect, are analytically calculated with geometric and process parameters in the local-level. As accurate values of the layout and process parameters are difficult to obtain, a set of model parameters is introduced to correct the errors caused by using these given inaccurate layout and process parameters at the local level. Scaling rules are defined to enable the formation of models that describe the behavior of the inductors of a variety of geometric dimensions. A series of asymmetric inductors with different geometries are fabricated on a standard 0.18-μm SiGe BiCMOS process with 100 Ω/cm substrate resistivity to verify the proposed model. Excellent agreement has been obtained between the measured results and the proposed model over a wide frequency range.
J. Semicond. 2012, 33(8): 085001
doi: 10.1088/1674-4926/33/8/085001Shi Jian, Mo Taishan, Le Jianlian, Gan Yebing, Ma Chengyan, Ye Tianchun. A high-efficiency, low-noise power solution for a dual-channel GNSS RF receiver[J]. 威尼斯人棋牌, 2012, 33(8): 085001. doi: 10.1088/1674-4926/33/8/085001.
Shi J, Mo T S, Le J L, Gan Y B, Ma C Y, Ye T C. A high-efficiency, low-noise power solution for a dual-channel GNSS RF receiver[J]. J. Semicond., 2012, 33(8): 085001. doi: 10.1088/1674-4926/33/8/085001.Export: BibTex EndNote
A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented. The power solution involves a DC-DC buck converter and a followed low-dropout regulator (LDO). The pulse-width-modulation (PWM) control method is adopted for better noise performance. An improved low-power high-frequency PWM control circuit is proposed, which halves the average quiescent current of the buck converter to 80 μA by periodically shutting down the OTA. The size of the output stage has also been optimized to achieve high efficiency under a light load condition. In addition, a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current. Fabricated with commercial 180-nm CMOS technology, the DC-DC converter achieves a peak efficiency of 93.1% under a 2 MHz working frequency. The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.
J. Semicond. 2012, 33(8): 085002
doi: 10.1088/1674-4926/33/8/085002Li Yuanqing, Yao Suying, Xu Jiangtao, Gao Jing. An SEU-hardened latch with a triple-interlocked structure[J]. 威尼斯人棋牌, 2012, 33(8): 085002. doi: 10.1088/1674-4926/33/8/085002.
Li Y Q, Yao S Y, Xu J T, Gao J. An SEU-hardened latch with a triple-interlocked structure[J]. J. Semicond., 2012, 33(8): 085002. doi: 10.1088/1674-4926/33/8/085002.Export: BibTex EndNote
A single event upset (SEU) tolerant latch with a triple-interlocked structure is presented. Its self-recovery mechanism is implemented by using three pairs of guard-gates and inverters to construct feedback lines inside the structure. This latch effectively suppresses the effects of charge deposition at any single internal node caused by particle strikes. Three recently reported SEU-hardened latches are chosen and compared with this latch in terms of reliability. The potential problems that these three latches could still get flipped due to single event effects or single event effects plus crosstalk coupling are pointed out, which can be mitigated by this proposed latch. The SEU tolerance of each latch design is evaluated through circuit-level SEU injection simulation. Furthermore, discussions on the crosstalk robustness and some other characteristics of these latches are also presented.
A 10-Gb/s inductor-less variable gain amplifier with a linear-in-dB characteristic and DC-offset cancellation
J. Semicond. 2012, 33(8): 085003
doi: 10.1088/1674-4926/33/8/085003Liu Chang, Yan Yuepeng, Goh Wang-Ling, Xiong Yongzhong, Zhang Lijun, Mohammad Madihian. A 10-Gb/s inductor-less variable gain amplifier with a linear-in-dB characteristic and DC-offset cancellation[J]. 威尼斯人棋牌, 2012, 33(8): 085003. doi: 10.1088/1674-4926/33/8/085003.
Liu C, Yan Y P, Goh W, Xiong Y Z, Zhang L J, Mohammad M. A 10-Gb/s inductor-less variable gain amplifier with a linear-in-dB characteristic and DC-offset cancellation[J]. J. Semicond., 2012, 33(8): 085003. doi: 10.1088/1674-4926/33/8/085003.Export: BibTex EndNote
This paper presents a broadband inductor-less variable gain amplifier (VGA) with a linear-in-dB gain control characteristic and DC-offset cancellation. The proposed VGA is composed of a variable gain block, an exponential voltage generator, a DC-offset canceller with common-mode voltage correction, and a gain peaking block. To achieve the broad band and reduce the chip area, the gain peaking block employs an inductor-less gain peaking scheme to compensate the high frequency gain drop of the variable gain block and the DC-offset canceller. The VGA fabricated in 0.13 μm SiGe BiCMOS technology achieves a 3-dB bandwidth of 7.5 GHz and a variable gain range from -10 to 30 dB. Due to the inductor-less design, the die area is only 0.53 × 0.27 mm2 which is the smallest among other similar reported works. At 10-Gb/s, the VGA consumes 50 mW power from a single 1.2 V supply and exhibits an output data jitter of less than 30 pspp.
J. Semicond. 2012, 33(8): 085004
doi: 10.1088/1674-4926/33/8/085004Zhou Chunyuan, Zhang Lei, Wang Hongrui, Qian He. A CMOS frequency generation module for 60-GHz applications[J]. 威尼斯人棋牌, 2012, 33(8): 085004. doi: 10.1088/1674-4926/33/8/085004.
Zhou C Y, Zhang L, Wang H R, Qian H. A CMOS frequency generation module for 60-GHz applications[J]. J. Semicond., 2012, 33(8): 085004. doi: 10.1088/1674-4926/33/8/085004.Export: BibTex EndNote
A frequency generation module for 60-GHz transceivers and phased array systems is presented in this paper. It is composed of a divide-by-2 current mode logic divider (CML) and a doubler in push-push configuration. Benefiting from the CML structure and push-push configuration, the proposed frequency generation module has a wide operating frequency range to cover process, voltage, and temperature variation. It is implemented in a 90-nm CMOS process, and occupies a chip area of 0.64 × 0.65 mm2 including pads. The measurement results show that the designed frequency generation module functions properly with input frequency over 15 GHz to 25 GHz. The whole chip dissipates 12.1 mW from a 1.2-V supply excluding the output buffers.
J. Semicond. 2012, 33(8): 085005
doi: 10.1088/1674-4926/33/8/085005Wang Haishi, Zhang Bo, Sun Jiang. Ways to suppress click and pop for class D amplifiers[J]. 威尼斯人棋牌, 2012, 33(8): 085005. doi: 10.1088/1674-4926/33/8/085005.
Wang H S, Zhang B, Sun J. Ways to suppress click and pop for class D amplifiers[J]. J. Semicond., 2012, 33(8): 085005. doi: 10.1088/1674-4926/33/8/085005.Export: BibTex EndNote
Undesirable audio click and pop may be generated in a speaker or headphone. Compared to linear (class A/B/AB) amplifiers, class D amplifiers that comprise of an input stage and a modulation stage are more prone to producing click and pop. This article analyzes sources that generate click and pop in class D amplifiers, and corresponding ways to suppress them. For a class D amplifier with a single-ended input, click and pop is likely to be due to two factors. One is from a voltage difference (VDIF) between the voltage of an input capacitance (VCIN) and a reference voltage (VREF) of the input stage, and the other one is from the non-linear switching during the setting up of the bias and feedback voltages/currents (BFVC) of the modulation stage. In this article, a fast charging loop is introduced into the input stage to charge VCIN to roughly near VREF. Then a correction loop further charges or discharges VCIN, substantially equalizing it with VREF. Dummy switches are introduced into the modulation stage to provide switching signals for setting up BFVC, and the power switches are disabled until the BFVC are set up successfully. A two channel single-ended class D amplifier with the above features is fabricated with 0.5 μm Bi-CMOS process. Road test and fast Fourier transform analysis indicate that there is no noticeable click and pop.
J. Semicond. 2012, 33(8): 085006
doi: 10.1088/1674-4926/33/8/085006Wang Shaopeng, Ren Yannan, Li Fule, Wang Zhihua. A 400-MS/s 12-bit current-steering D/A converter[J]. 威尼斯人棋牌, 2012, 33(8): 085006. doi: 10.1088/1674-4926/33/8/085006.
Wang S P, Ren Y N, Li F L, Wang Z H. A 400-MS/s 12-bit current-steering D/A converter[J]. J. Semicond., 2012, 33(8): 085006. doi: 10.1088/1674-4926/33/8/085006.Export: BibTex EndNote
This paper presents a 400-MS/s 12-bit CMOS current-steering digital-to-analog converter (DAC). The proposed DAC adapts 6+2+4 segmented architecture and a modified switching scheme to improve dynamic and static performance. The measured spurious-free dynamic range is up to 77.18 dB at 400 MS/s with a 10 MHz input signal. The full-scale output current is 20 mA with a 1.8 V single power supply. The core area occupies 0.6 mm2 in a standard 1P-6M 0.18-μm CMOS process.
J. Semicond. 2012, 33(8): 085007
doi: 10.1088/1674-4926/33/8/085007Deng Yong, Shi Yibing, Zhang Wei. Diagnosis of soft faults in analog integrated circuits based on fractional correlation[J]. 威尼斯人棋牌, 2012, 33(8): 085007. doi: 10.1088/1674-4926/33/8/085007.
Deng Y, Shi Y B, Zhang W. Diagnosis of soft faults in analog integrated circuits based on fractional correlation[J]. J. Semicond., 2012, 33(8): 085007. doi: 10.1088/1674-4926/33/8/085007.Export: BibTex EndNote
Aiming at the problem of diagnosing soft faults in analog integrated circuits, an approach based on fractional correlation is proposed. First, the Volterra series of the circuit under test (CUT) decomposed by the fractional wavelet packet are used to calculate the fractional correlation functions. Then, the calculated fractional correlation functions are used to form the fault signatures of the CUT. By comparing the fault signatures, the different soft faulty conditions of the CUT are identified and the faults are located. Simulations of benchmark circuits illustrate the proposed method and validate its effectiveness in diagnosing soft faults in analog integrated circuits.
J. Semicond. 2012, 33(8): 085008
doi: 10.1088/1674-4926/33/8/085008Han Lei, Wang Yujun, Zhang Xiaoxing, Dai Yujie, Lü Yingjie. A simple and effective method to achieve the successful start-up of a current reference[J]. 威尼斯人棋牌, 2012, 33(8): 085008. doi: 10.1088/1674-4926/33/8/085008.
Han L, Wang Y J, Zhang X X, Dai Y J, Lü Y J. A simple and effective method to achieve the successful start-up of a current reference[J]. J. Semicond., 2012, 33(8): 085008. doi:?10.1088/1674-4926/33/8/085008.Export: BibTex EndNote
Start-up design is a critical issue in current reference as it is very closely related to production yield. However, its function is difficult to predict using normal transaction simulations before the device is put into diffusion. In this paper, we discuss a simple and effective simulation approach which ensures a successful start-up process in a self-biased temperature independent current reference. The circuit is implemented in a class-D power amplifier with a 0.35 μm BiCMOS process and the experimental result validates that, by using this method, the start-up success rate can be greatly improved to 100%.
J. Semicond. 2012, 33(8): 086001
doi: 10.1088/1674-4926/33/8/086001Ruan Wenbiao, Chen Lan, Ma Tianyu, Fang Jingjing, Zhang He, Ye Tianchun. Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits[J]. 威尼斯人棋牌, 2012, 33(8): 086001. doi: 10.1088/1674-4926/33/8/086001.
Ruan W B, Chen L, Ma T Y, Fang J J, Zhang H, Ye T C. Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits[J]. J. Semicond., 2012, 33(8): 086001. doi: 10.1088/1674-4926/33/8/086001.Export: BibTex EndNote
A copper chemical mechanical polishing (Cu CMP) process is reviewed and analyzed from the view of chemical physics. Three steps Cu CMP process modeling is set up based on the actual process of manufacturing and pattern-density-step-height (PDSH) modeling from MIT. To catch the pattern dependency, a 65 nm testing chip is designed and processed in the foundry. Following the model parameter extraction procedure, the model parameters are extracted and verified by testing data from the 65 nm testing chip. A comparison of results between the model predictions and test data show that the former has the same trend as the latter and the largest deviation is less than 5 nm. Third party testing data gives further evidence to support the great performance of model parameter optimization. Since precise CMP process modeling is used for the design of manufacturability (DFM) checks, critical hotspots are displayed and eliminated, which will assure good yield and production capacity of IC.
J. Semicond. 2012, 33(8): 086002
doi: 10.1088/1674-4926/33/8/086002He Ran, Wang Huijuan, Yu Daquan, Zhou Jing, Dai Fengwei, Song Chongshen, Sun Yu, Wan Lixi. High-speed through-silicon via filling method using Cu-cored solder balls[J]. 威尼斯人棋牌, 2012, 33(8): 086002. doi: 10.1088/1674-4926/33/8/086002.
He R, Wang H J, Yu D Q, Zhou J, Dai F W, Song C S, Sun Y, Wan L X. High-speed through-silicon via filling method using Cu-cored solder balls[J]. J. Semicond., 2012, 33(8): 086002. doi: 10.1088/1674-4926/33/8/086002.Export: BibTex EndNote
A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture. Cu-cored solder balls with a total diameter of 100 μm were used to fill 150 μm deep, 110 μm wide vias in silicon. The wafer-level filling process can be completed in a few seconds, which is much faster than using the traditional electroplating process. Thermo-mechanical analysis of via filling using solder, Cu and Cu-cored solder was carried out to assess the thermo-mechanical properties of the different filling materials. It was found that the vias filled with Cu-cored solder exhibit less thermal-mechanical stresses than solder-filled vias, but more than Cu-filled vias.
INVITED REVIEW PAPERS
SEMICONDUCTOR INTEGRATED CIRCUITS