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Volume 33, Issue 10, Oct 2012

    SEMICONDUCTOR PHYSICS

  • Radiation effect on the optical and electrical properties of CdSe(In)/p-Si heterojunction photovoltaic solar cells

    M. Ashry, S. Fares

    J. Semicond.  2012, 33(10): 102001

    doi: 10.1088/1674-4926/33/10/102001

    Abstract PDF Get Citation

    The efficiency and radiation resistance of solar cells are graded. They are then fabricated in the form of n-CdeSe(In)/p-Si heterojunction cells by electron beam evaporation of a stoichiomteric mixture of CdSe and In to make a thin film on a p-Si single crystal wafer with a thickness of 100 μm and a resistivity of ~ 1.5 Ω·cm at a temperature of 473 K. The short-circuit current density (jsc), open-circuit voltage (Voc), fill factor (ff) and conversion efficiency (η) under 100 mW/cm2 (AM1) intensity, are 20 mA/cm2, 0.49 V, 0.71 and 6% respectively. The cells were exposed to different electron doses (electron beam accelerator of energy 1.5 MeV, and beam intensity 25 mA). The cell performance parameters are measured and discussed before and after gamma and electron beam irradiation.

  • Protection effect of a SiO2 layer in Al0.85Ga0.15As wet oxidation

    Zhou Wenfei, Ye Xiaoling, Xu Bo, Zhang Shizhu, Wang Zhanguo

    J. Semicond.  2012, 33(10): 102002

    doi: 10.1088/1674-4926/33/10/102002

    Abstract PDF Get Citation

    The Al0.85Ga0.15As layers buried below the GaAs core layer with and without the SiO2 layer were successfully oxidized in a wet ambient environment. The experimental results show that the SiO2 layer has little impact on the lateral-wet-oxidation rate of the Al0.85Ga0.15As layer. The contrast of the SEM image of the oxidized regions and the absence of As-related Raman peaks for samples with the SiO2 layer arise from the removal of As ingredients with the largest atomic number, which leads to improvements in the thermal stability of the oxidized layer. The PL intensities of samples with the SiO2 layer are much stronger than those without the SiO2 layer. The PL emission peak is almost unshifted with a slight broadening under the protection of the SiO2 layer. This is attributed to the SiO2 layer preventing oxidation damage to the GaAs capping layer.

  • Dry etching of new phase-change material Al1.3Sb3Te in CF4/Ar plasma

    Zhang Xu, Rao Feng, Liu Bo, Peng Cheng, Zhou Xilin, Yao Dongning, Guo Xiaohui, Song Sanniang, Wang Liangyong, Cheng Yan, Wu Liangcai, Song Zhitang, Feng Songlin

    J. Semicond.  2012, 33(10): 102003

    doi: 10.1088/1674-4926/33/10/102003

    Abstract PDF Get Citation

    The dry etching characteristic of Al1.3Sb3Te film was investigated by using a CF4/Ar gas mixture. The experimental control parameters were gas flow rate into the chamber, CF4/Ar ratio, the O2 addition, the chamber background pressure, and the incident RF power applied to the lower electrode. The total flow rate was 50 sccm and the behavior of etch rate of Al1.3Sb3Te thin films was investigated as a function of the CF4/Ar ratio, the O2 addition, the chamber background pressure, and the incident RF power. Then the parameters were optimized. The fast etch rate was up to 70.8 nm/min and a smooth surface was achieved using optimized etching parameters of CF4 concentration of 4%, power of 300 W and pressure of 80 mTorr.

  • Fermi level depinning by a C-containing layer in a metal/Ge structure by using a chemical bath

    Wang Wei, Wang Jing, Zhao Mei, Liang Renrong, Xu Jun

    J. Semicond.  2012, 33(10): 102004

    doi: 10.1088/1674-4926/33/10/102004

    Abstract PDF Get Citation

    Insertion of a C-containing layer in a metal/Ge structure, using a chemical bath, enabled the Schottky barrier height (SBH) to be modulated. Chemical baths with 1-octadecene, 1-hexadecene, 1-tetradecene, and 1-dodecene were used separately with Ge substrates. An ultrathin C-containing layer stops the penetration of free electron wave functions from the metal to the Ge. Metal-induced gap states are alleviated and the pinned Fermi level is released. The SBH is lowered to 0.17 eV. This new formation method is much less complex than traditional ones, and the result is very good.

  • SEMICONDUCTOR MATERIALS

  • Effects of growth temperature on high-quality In0.2Ga0.8N layers by plasma-assisted molecular beam epitaxy

    Zhang Dongyan, Zheng Xinhe, Li Xuefei, Wu Yuanyuan, Wang Jianfeng, Yang Hui

    J. Semicond.  2012, 33(10): 103001

    doi: 10.1088/1674-4926/33/10/103001

    Abstract PDF Get Citation

    High-quality In0.2Ga0.8N epilayers were grown on a GaN template at temperatures of 520 and 580℃ via plasma-assisted molecular beam epitaxy. The X-ray rocking curve full widths at half maximum (FWHM) of (10.2) reflections is 936 arcsec for the 50-nm-thick InGaN layers at the lower temperature. When the growth temperature increases to 580℃, the FWHM of (00.2) reflections for these samples is very narrow and keeps similar, while significant improvement of (10.2) reflections with an FWHM value of 612 arcsec has been observed. This improved quality in InGaN layers grown at 580℃ is also reflected by the much larger size of the crystalline column from the AFM results, stronger emission intensity as well as a decreased FWHM of room temperature PL from 136 to 93.9 meV.

  • An aluminum nitride photoconductor for X-ray detection

    Wang Xinjian, Song Hang, Li Zhiming, Jiang Hong, Li Dabing, Miao Guoqing, Chen Yiren, Sun Xiaojuan

    J. Semicond.  2012, 33(10): 103002

    doi: 10.1088/1674-4926/33/10/103002

    Abstract PDF Get Citation

    An AlN photoconductor for X-ray detection has been fabricated, and its response to X-ray irradiation intensity is studied. The photoconductor has a very low leakage current, less than 0.1 nA at an applied voltage of 100 V in the absence of X-ray irradiation. The photocurrent measurement results clearly reveal that the photocurrent is proportional to the square root of the X-ray irradiation intensity, and under relatively high irradiation the photocurrent can reach values one order of magnitude larger than the dark current when a voltage of 100 V is applied across the AlN photoconductor. By using the ABC model the dependence of the photocurrent on the X-ray irradiation intensity is analyzed, and a reasonable interpretation of the physical mechanism is obtained.

  • SEMICONDUCTOR DEVICES

  • An InP-based heterodimensional Schottky diode for terahertz detection

    Wen Ruming, Sun Hao, Teng Teng, Li Lingyun, Sun Xiaowei

    J. Semicond.  2012, 33(10): 104001

    doi: 10.1088/1674-4926/33/10/104001

    Abstract PDF Get Citation

    We present an InP-based heterodimensional Schottky diode (HDSD), which has so far never been reported in the literature. Compared to a GaAs-based HDSD, the InP-based HDSD is expected to have better high frequency performance and operational conditions resulting from its higher mobility and concentration of 2D electron gas (2DEG) as well as its smaller Schottky barrier height. The cutoff frequency of the InP-based HDSD obtained by the AC measurement is more than 500 GHz, which shows its potential application in terahertz detection.

  • Improved ESD characteristic of GaN-based blue light-emitting diodes with a low temperature n-type GaN insertion layer

    Li Panpan, Li Hongjian, Zhang Yiyun, Li Zhicong, Liang Meng, Li Jing, Wang Guohong

    J. Semicond.  2012, 33(10): 104002

    doi: 10.1088/1674-4926/33/10/104002

    Abstract PDF Get Citation

    We demonstrate the improvement of the electrostatic discharge (ESD) characteristic of GaN-based blue light-emitting diodes (LEDs) by inserting a low-temperature n-type GaN (LT-nGaN) layer between the n-type GaN layer and InGaN/GaN multiple quantum wells (MQWs). The ESD endurance voltage > 4000 V pass yield is increased from 9.9% to 74.7% when the LT-nGaN insertion layer is applied to the GaN/sapphire-based LEDs. The LT-nGaN plays a role of buffer layer for MQWs, which reduces the strain of MQWs and improves the interface quality. Moreover, we also demonstrate that ESD characteristics of the LEDs with LT-nGaN insertion layer growth in N2 aremuch better than that in H2, which further confirm that the improvement of ESD characteristics is due to thestrain relaxation in MQWs. Optoelectrical measurements show that there is no deterioration of the electrical properties of LEDs and the light output power of LEDs at an injection current of 20 mA is improved by 13.9%.

  • High voltage SOI LDMOS with a compound buried layer

    Luo Xiaorong, Hu Gangyi, Zhou Kun, Jiang Yongheng, Wang Pei, Wang Qi, Luo Yinchun, Zhang Bo, Li Zhaoji

    J. Semicond.  2012, 33(10): 104003

    doi: 10.1088/1674-4926/33/10/104003

    Abstract PDF Get Citation

    An SOI LDMOS with a compound buried layer (CBL) was proposed. The CBL consists of an upper buried oxide layer (UBOX) with a Si window and two oxide steps, a polysilicon layer and a lower buried oxide layer (LBOX). In the blocking state, the electric field strengths in the UBOX and LBOX are increased from 88 V/μm of the buried oxide (BOX) in a conventional SOI (C-SOI) LDMOS to 163 V/μm and 460 V/μm by the holes located on the top interfaces of the UBOX and LBOX, respectively. Compared with the C-SOI LDMOS, the CBL LDMOS increases the breakdown voltage from 477 to 847 V, and lowers the maximal temperature by 6 K.

  • Simulation of cold plasma in a chamber under high- and low-frequency voltage conditions for a capacitively coupled plasma

    Hao Daoxin, Cheng Jia, Ji Linhong, Sun Yuchun

    J. Semicond.  2012, 33(10): 104004

    doi: 10.1088/1674-4926/33/10/104004

    Abstract PDF Get Citation

    The characteristics of cold plasma, especially for a dual-frequency capacitively coupled plasma (CCP), play an important role for plasma enhanced chemical vapor deposition, which stimulates further studies using different methods. In this paper, a 2D fluid model was constructed for N2 gas plasma simulations with CFD-ACE+, a commercial multi-physical software package. First, the distributions of electric potential (Epot), electron number density (Ne), N number density (N) and electron temperature (Te) are described under the condition of high frequency (HF), 13.56 MHz, HF voltage, 300 V, and low-frequency (LF) voltage, 0 V, particularly in the sheath. Based on this, the influence of HF on Ne is further discussed under different HF voltages of 200 V, 300 V, 400 V, separately, along with the influence of LF, 0.3 MHz, and various LF voltages of 500 V, 600 V, 700 V. The results show that sheaths of about 3 mm are formed near the two electrodes, in which Epot and Te vary extensively with time and space, while in the plasma bulk Epot changes synchronously with an electric potential of about 70 V and Te varies only in a small range. N is also modulated by the radio frequency, but the relative change in N is small. Ne varies only in the sheath, while in the bulk it is steady at different time steps. So, by comparing Ne in the plasma bulk at the steady state, we can see that Ne will increase when HF voltage increases. Yet, Ne will slightly decrease with the increase of LF voltage. At the same time, the homogeneity will change in both x and y directions. So both HF and LF voltages should be carefully considered in order to obtain a high-density, homogeneous plasma.

  • Design and measurement of a piezoresistive triaxial accelerometer based on MEMS technology

    Du Chunhui, He Changde, Yu Jiaqi, Ge Xiaoyang, Zhang Yongping, Zhang Wendong

    J. Semicond.  2012, 33(10): 104005

    doi: 10.1088/1674-4926/33/10/104005

    Abstract PDF Get Citation

    With the springing up of the MEMS industry, research on accelerometers is focused on miniaturization, integration, high reliability, and high resolution, and shares extensive application prospects in military and civil fields. Comparing with the traditional single cantilever beam structure or "cantilever-mass" structure, the proposed structure of "8-beams/mass" with its varistor completely symmetric distribution in micro-silicon piezoresistive triaxial accelerometer in this paper has a higher axial sensitivity and smaller cross-axis sensitivity. Adopting ANSYS, the process of structural analysis and the manufacturing flow of sensing unit are showed. In dynamic testing conditions, it can be concluded that the axial sensitivity of x, y, and z are Sx=48 μV/g, Sy= 54 μV/g and Sz= 217 μV/g respectively, and the nonlinearities are 0.4%, 0.6% and 0.4%.

  • Contact size scaling of a W-contact phase-change memory cell based on numerical simulation

    Wei Yiqun, Lin Xinnan, Jia Yuchao, Cui Xiaole, Zhang Xing, Song Zhitang

    J. Semicond.  2012, 33(10): 104006

    doi: 10.1088/1674-4926/33/10/104006

    Abstract PDF Get Citation

    In the design of phase-change memory (PCM), it is important to perform numerical simulations to predict the performances of different device structures. This work presents a numerical simulation using a coupled system including Poisson's equation, the current continuity equation, the thermal conductivity equation, and phase-change dynamics to simulate the thermal and electric characteristics of phase-change memory. This method discriminates the common numerical simulation of PCM cells, from which it applies Possion's equation and current continuity equations instead of the Laplace equation to depict the electric characteristics of PCM cells, which is more adoptable for the semiconductor characteristics of phase-change materials. The results show that the simulation agrees with the measurement, and the scalability of PCM is predicted.

  • Effects of manufacturing errors on the characteristics of a polymer vertical coupling microring resonator

    Wang Yuhai, Qin Zhengkun, Wang Chunxu, Wang Lizhong

    J. Semicond.  2012, 33(10): 104007

    doi: 10.1088/1674-4926/33/10/104007

    Abstract PDF Get Citation

    The effects of manufacturing errors on transmission characteristics are analyzed for a polymer vertical coupling microring resonator. Calculated results show that the errors cause a shift and shape change of the transmission spectrum compared to the designed case without errors. Furthermore, accumulation and compensation for the errors is researched. In order to realize the normal filtering for the fabricated microring resonator device, some allowed errors are discussed.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • A low power 2.5-5 GHz low-noise amplifier using 0.5-μm GaAs pHEMT technology

    Peng Yangyang, Lu Kejie, Sui Wenquan

    J. Semicond.  2012, 33(10): 105001

    doi: 10.1088/1674-4926/33/10/105001

    Abstract PDF Get Citation

    A two-stage 2.5-5 GHz monolithic low-noise amplifier (LNA) has been fabricated using 0.5-μm enhanced mode AlGaAs/GaAs pHEMT technology. To achieve wide operation bandwidth and low noise figure, the proposed LNA uses a wideband matching network and a negative feedback technique. Measured results from 2.5 to 5 GHz demonstrate a minimum of 2.4-dB noise figure and 17-dB gain. The input and output return loss exceeded -10-dB across the band. The power consumption of this LNA is 33 mW. According to the author's knowledge, this is the lowest power consumption LNA fabricated in 0.5-μm AlGaAs/GaAs pHEMT with the comparable performance.

  • A high linearity downconverter for SAW-less LTE receivers

    Jiang Peichen, Guan Rui, Wang Wufeng, Chen Dongpo, Zhou Jianjun

    J. Semicond.  2012, 33(10): 105002

    doi: 10.1088/1674-4926/33/10/105002

    Abstract PDF Get Citation

    This paper presents a high linearity downconverter implemented in a 0.18 μm CMOS process for long term evolution (LTE) receivers without a surface acoustic wave (SAW) filter. The proposed downconverter is composed of a transconductance (Gm) stage, a passive mixer, a current buffer, a transimpedance (TIA) stage, and a DC-offset cancellation (DCOC) loop. The current buffer is utilized to provide very low load impedance for the passive mixer at high frequencies and reduce the output voltage swing induced by out-of-band blockers. This technique improves the input referred third-order intercept point (IIP3) and second-order intercept point (IIP2) of the downconverter by 4.5 dB and 11 dB, respectively. The measured results show that the proposed downconverter achieves a voltage conversion gain of 29.5 dB, double sideband noise figure of 12.7 dB, out-of-band IIP3 of 13 dBm and IIP2 of more than 62 dBm.

  • A CMOS AC/DC charge pump for a wireless sensor network

    Zhang Qiang, Ni Weining, Shi Yin, Yu Yude

    J. Semicond.  2012, 33(10): 105003

    doi: 10.1088/1674-4926/33/10/105003

    Abstract PDF Get Citation

    An AC/DC charge pump implemented with MOS FETs has been presented for wireless sensor network applications. The proposed AC/DC charge pump can generate a stable output with low power dissipation and high pumping efficiency, which has been implemented in 0.13 μm CMOS technology. The proposed charge pump employs MOSFET diodes with low thresholds (Vth), and improves the conversion efficiency. The analytical model of the voltage multiplier, the simulation results, and the chip testing results are presented.

  • A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

    Wang Xiaoyu, Yang Haigang, Li Fanyang, Yin Tao, Liu Fei

    J. Semicond.  2012, 33(10): 105004

    doi: 10.1088/1674-4926/33/10/105004

    Abstract PDF Get Citation

    A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC (automatic gain control) and a current-mode adaptive filter. Compared with its conventional voltage-mode counterparts, the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic. The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss. The continuous gain should meet the requirement of any input amplitude level, while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL (sound pressure level). Furthermore, the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility. These features can accommodate users whose ears have different pain thresholds. Taking advantage of the current-mode technique, the MOS transistors work in the subthreshold region so that the quiescent current is small. Moreover, the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain. Therefore, the objective of low voltage and low power (48 μW at 1.4 V) can be easily achieved in a high threshold-voltage CMOS process of 0.35 μm (VTON+|VTOP|≈1.35 V). The THD is below -45 dB. The fabricated chip only occupies the area of 1 × 0.5 mm2 and 1 × 1 mm2.

  • Design of low power common-gate low noise amplifier for 2.4 GHz wireless sensor network applications

    Zhang Meng, Li Zhiqun

    J. Semicond.  2012, 33(10): 105005

    doi: 10.1088/1674-4926/33/10/105005

    Abstract PDF Get Citation

    This paper presents a differential low power low noise amplifier designed for the wireless sensor network (WSN) in a TSMC 0.18 μm RF CMOS process. A two-stage cross-coupling cascaded common-gate (CG) topology has been designed as the amplifier. The first stage is a capacitive cross-coupling topology. It can reduce the power and noise simultaneously. The second stage is a positive feedback cross-coupling topology, used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA. A differential inductor has been designed as the load to achieve reasonable gain. This inductor has been simulated by the means of momentum electromagnetic simulation in ADS. A "double-π" circuit model has been built as the inductor model by iteration in ADS. The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured. The LNA works well centered at 2.44 GHz. The measured gain S21 is variable with high gain at 16.8 dB and low gain at 1 dB. The NF (noise figure) at high gain mode is 3.6 dB, the input referenced 1 dB compression point (IP1dB) is about -8 dBm and the IIP3 is 2 dBm at low gain mode. The LNA consumes about 1.2 mA current from 1.8 V power supply.

  • A 7-27 GHz DSCL divide-by-2 frequency divider

    Guo Ting, Li Zhiqun, Li Qin, Wang Zhigong

    J. Semicond.  2012, 33(10): 105006

    doi: 10.1088/1674-4926/33/10/105006

    Abstract PDF Get Citation

    This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic (DSCL) structure formed with two dynamic-loading master-slave D latches, which enables high frequency operation and low power consumption. This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply. The input sensitivity is as low as -25.4 dBm across the operating frequency range. This chip occupies 685 × 430 μm2 area with two on-chip spiral inductors in 90 nm CMOS process.

  • A single-event-hardened phase-locked loop using the radiation-hardened-by-design technique

    Han Benguang, Guo Zhongjie, Wu Longsheng, Liu Youbao

    J. Semicond.  2012, 33(10): 105007

    doi: 10.1088/1674-4926/33/10/105007

    Abstract PDF Get Citation

    A radiation-hardened-by-design phase-locked loop (PLL) with a frequency range of 200 to 1000 MHz is proposed. By presenting a novel charge compensation circuit, composed by a lock detector circuit, two operational amplifiers, and four MOS devices, the proposed PLL significantly reduces the recovery time after the presence of a single event transient (SET). Comparing with many traditional hardened methods, most of which endeavor to enhance the immunity of the charge pump output node to an SET, the novel PLL can also decrease its susceptibility in the presence of an SET in other blocks. A novel system model is presented to describe immunity of a PLL to an SET and used to compare the sensitivity of traditional and hardened PLLs to an SET. An SET is simulated on Sentaurus TCAD simulation workbench to model the induced pulse current. Post simulation with a 130 nm CMOS process model shows that the recovery time of the proposed PLL reduces by up to 93.5% compared with the traditional one, at the same time, the charge compensation circuit adds no complexity to the systemic parameter design.

  • A wideband LC-VCO with small VCO gain variation and adaptive power control

    Li Bin, Fan Xiangning, Wang Zhigong

    J. Semicond.  2012, 33(10): 105008

    doi: 10.1088/1674-4926/33/10/105008

    Abstract PDF Get Citation

    A wideband LC tank voltage-controlled-oscillator (VCO) is proposed. To solve the impacts of wideband operation on VCO gain (KVCO) variation and start-up constraint, a binary-weighted varactor array and a binary-weighted negative resistance array all with optimal unit values are designed. Implemented in a 0.18 μm CMOS process, the proposed VCO shows a frequency tuning range from 1.9 to 3.1 GHz, with a current consumption varying accordingly from 14.2 to 4 mA from a 1.8 V supply. With the proposed KVCO suppression technique, the KVCO varies from 50 to 60 MHz/V in the entire frequency range. The measured phase noise is -117 dBc/Hz at a 1 MHz offset from a 3 GHz carrier.

  • Design and optimization of a 0.5 V CMOS LNA for 2.4-GHz WSN application

    Chen Liang, Li Zhiqun

    J. Semicond.  2012, 33(10): 105009

    doi: 10.1088/1674-4926/33/10/105009

    Abstract PDF Get Citation

    This paper presents a low noise amplifier (LNA), which could work at an ultra-low voltage of 0.5 V and was optimized for WSN application using 0.13 μm RF-CMOS technology. The circuit was analyzed and a new optimization method for a folded cascode LNA was introduced. Measured results of the proposed circuit demonstrated a power gain of 14.13 dB, consuming 3 mW DC power, showing 1.96 dB NF and an input 1-dB compression point of -19.9 dBm. Both input power matching (S11) and output power matching (S22) were below -10 dB. The results indicate that this LNA is fully applicable to low voltage and low power applications.

  • A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration

    Zhang Yiwen, Chen Chixiao, Yu Bei, Ye Fan, Ren Junyan

    J. Semicond.  2012, 33(10): 105010

    doi: 10.1088/1674-4926/33/10/105010

    Abstract PDF Get Citation

    Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters (TIADCs). A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper. The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals. The detected sample-time error is corrected by a voltage-controlled sampling switch. The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB, and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration. The calibration convergence time is about 20000 sampling intervals.

  • Design and implementation of a 3-A source and sink linear regulator for bus terminators

    Li Yanming, Mao Xiangyu, Wen Changbao, Wen Limin

    J. Semicond.  2012, 33(10): 105011

    doi: 10.1088/1674-4926/33/10/105011

    Abstract PDF Get Citation

    According to the requirements of the bus terminal regulator, a linear regulator with 3-A source-sink current ability is presented. The use of the NMOS pass transistor and load current feedback technique enhances the system current ability and response speed. The method of adaptive zero compensation realizes loop stability over the whole load range for either source or sink loop. Furthermore, the transconductance matching technique reduces the shoot-through current through the output stage to less than 3 μA. The regulator has been fabricated with a 0.6-μm 30 V BCD process successfully, and the area size is about 1 mm2. With a 20 μF output capacitor, the maximum transient output-voltage variation is within 3.5% of the output voltage with load step changes of ±2 A/1 μs. At the load range of ±3 A, the variation of output voltage is less than ±15 mV.

  • Design and implementation of channel estimation for low-voltage power line communication systems based on OFDM

    Zhao Huidong, Hei Yong, Qiao Shushan, Ye Tianchun

    J. Semicond.  2012, 33(10): 105012

    doi: 10.1088/1674-4926/33/10/105012

    Abstract PDF Get Citation

    An optimized channel estimation algorithm based on a time-spread structure in OFDM low-voltage power line communication (PLC) systems is proposed to achieve a lower bit error rate (BER). This paper optimizes the best maximum multi-path delay of the linear minimum mean square error (LMMSE) algorithm in time-domain spread OFDM systems. Simulation results indicate that the BER of the improved method is lower than that of conventional LMMSE algorithm, especially when the signal-to-noise ratio (SNR) is lower than 0 dB. Both the LMMSE algorithm and the proposed algorithm are implemented and fabricated in CSMC 0.18 μm technology. This paper analyzes and compares the hardware complexity and performance of the two algorithms. Measurements indicate that the proposed channel estimator has better performance than the conventional estimator.

  • SEMICONDUCTOR TECHNOLOGY

  • Spatial control based quantum well intermixing in InP/InGaAsP structures using ICP

    Zhao Jianyi, Guo Jian, Huang Xiaodong, Zhou Ning, Liu Wen

    J. Semicond.  2012, 33(10): 106001

    doi: 10.1088/1674-4926/33/10/106001

    Abstract PDF Get Citation

    This paper presents a new method based on spatial controlling in quantum well intermixing in InP/InGaAsP structures using ICP technology. The degree of bandgap energy shift in the same wafer can be controlled flexibly using masks with different duty ratios. With an optimal condition including ICP-RIE etching depth, SiO2 deposition, and RTA process, five different degrees of blue-shift with maximum of 75 nm were obtained in the same sample. The result shows that our method is an effective way to fabricate monolithic integration devices, especially in multi-bandgap structures.

  • Key process study in nanoimprint lithography

    Wang Zhihao, Liu Wen, Wang Lei, Zuo Qiang, Zhao Yanli

    J. Semicond.  2012, 33(10): 106002

    doi: 10.1088/1674-4926/33/10/106002

    Abstract PDF Get Citation

    Nanoimprint lithography (NIL) is widely used in the fabrication of nano-scale semiconductor devices for its advantages of high resolution, low cost, and high throughput. However, traditional hard stamp imprinting has some drawbacks such as short stamp lifetime, bad uniformity in big areas, and large particle influence. In this paper, a flexible intermediate polymer stamp (IPS) is proposed to solve the drawbacks mentioned above. Meanwhile, we use a method of temperature-pressure variation imprinting to improve the resist liquidity in the process of imprinting, and eventually we achieve high quality patterns. This method combined with IPS has been used to fabricate a high quality grating whose half pitch is 50 nm.

  • Material removal rate of 6H-SiC crystal substrate CMP using an alumina (Al2O3) abrasive

    Su Jianxiu, Du Jiaxi, Zhang Zhuqing, Kang Renke

    J. Semicond.  2012, 33(10): 106003

    doi: 10.1088/1674-4926/33/10/106003

    Abstract PDF Get Citation

    The influences of the polishing slurry composition, such as the pH value, the abrasive size and its concentration, the dispersant and the oxidants, the rotational velocity of the polishing platen and the carrier and the polishing pressure, on the material removal rate of SiC crystal substrate (0001) Si and a (0001) C surface have been studied based on the alumina abrasive in chemical mechanical polishing (CMP). The results proposed by our research here will provide a reference for developing the slurry, optimizing the process parameters, and investigating the material removal mechanism in the CMP of SiC crystal substrate.

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