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Volume 32, Issue 7, Jul 2011

    SEMICONDUCTOR PHYSICS

  • Photoconductive properties of organic-inorganic Ag/p-CuPc/n-GaAs/Ag cell

    Khasan Sanginovich Karimov, Muhammad Tariq Saeed, Fazal Ahmad Khalid, Zioda Mirzoevna Karieva

    J. Semicond.  2011, 32(7): 072001

    doi: 10.1088/1674-4926/32/7/072001

    Abstract PDF Get Citation

    A thin film of copper phthalocyanine (CuPc) a p-type semiconductor was deposited by thermal evaporation in vacuum on an n-type gallium arsenide (GaAs) single-crystal semiconductor substrate. Then semitransparent Ag thin film was deposited on to the CuPc film also by thermal evaporation to fabricate the Ag/n-GaAs/p-CuPc/Ag cell. Photoconduction of the cell was measured in photoresistive and photodiode modes of operation. It was observed that with increase of illumination the photoresistance decreased in reverse bias while it increased in forward bias. The photocurrent was increased in reverse bias operation. In forward bias operation with increase of illumination the photocurrent showed a different behavior depending on the voltage applied.

  • Effect of annealing process on the surface roughness in multiple Al implanted 4H-SiC

    Wu Hailei, Sun Guosheng, Yang Ting, Yan Guoguo, Wang Lei, Zhao Wanshun, Liu Xingfang, Zeng Yiping, Wen Jialiang

    J. Semicond.  2011, 32(7): 072002

    doi: 10.1088/1674-4926/32/7/072002

    Abstract PDF Get Citation

    A P-layer can be formed on a SiC wafer surface by using multiple Al ion implantations and post-implantation annealing in a low pressure CVD reactor. The Al depth profile was almost box shaped with a height of 1 × 1019 cm-3 and a depth of 550 nm. Three different annealing processes were developed to protect the wafer surface. Variations in RMS roughness have been measured and compared with each other. The implanted SiC, annealed with a carbon cap, maintains a high-quality surface with an RMS roughness as low as 3.8 nm. Macrosteps and terraces were found in the SiC surface, which annealed by the other two processes (protect in Ar/protect with SiC capped wafer in Ar). The RMS roughness is 12.2 nm and 6.6 nm, respectively.

  • SEMICONDUCTOR MATERIALS

  • Effect of current on the microstructure and performance of (Bi2Te3)0.2(Sb2Te3)0.8 thermoelectric material via field activated and pressure assisted sintering

    Chen Ruixue, Meng Qingsen, Fan Wenhao, Wang Zhong

    J. Semicond.  2011, 32(7): 073001

    doi: 10.1088/1674-4926/32/7/073001

    Abstract PDF Get Citation

    (Bi2Te3)0.2(Sb2Te3)0.8 thermoelectric material was sintered via a field activated and pressure assisted sintering (FAPAS) process. By applying different current intensity (0, 60, 320 A/cm2) in the sintering process, the effects of electric current on the microstructure and thermoelectric performance were investigated. This demonstrated that the application of electric current in the sintering process could significantly improve the uniformity and density of (Bi2Te3)0.2(Sb2Te3)0.8 samples. When the current intensity was raised to 320 A/cm2, the preferred orientation of grains was observed. Moreover, positive effects on the thermoelectric performance of applying electric current in the sintering process were also confirmed. An increase of 0.02 and 0.11 in the maximum figure of merit ZT value could be acquired by applying current of 60 and 320 A/cm2, respectively.

  • SEMICONDUCTOR DEVICES

  • Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

    Ashwani K. Rana, Narottam Chand, Vinod Kapoor

    J. Semicond.  2011, 32(7): 074001

    doi: 10.1088/1674-4926/32/7/074001

    Abstract PDF Get Citation

    In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the ?rst time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

  • New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs

    Li Cong, Zhuang Yiqi, Han Ru

    J. Semicond.  2011, 32(7): 074002

    doi: 10.1088/1674-4926/32/7/074002

    Abstract PDF Get Citation

    Using an exact solution of two-dimensional Poisson's equation in cylindrical coordinates, a new analytical model comprising electrostatic potential, electric field, threshold voltage and subthreshold current for halo-doped surrounding-gate MOSFETs is developed. It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide. It is also revealed that moderate halo doping concentration, thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics. The derived analytical model agrees well with a three-dimensional numerical device simulator ISE.

  • Characteristics and optimization of 4H-SiC MESFET with a novel p-type spacer layer incorporated with a field-plate structure based on improved trap models

    Song Kun, Chai Changchun, Yang Yintang, Jia Hujun, Zhang Xianjun, Chen Bin

    J. Semicond.  2011, 32(7): 074003

    doi: 10.1088/1674-4926/32/7/074003

    Abstract PDF Get Citation

    A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression. Characteristics of the device have been investigated based on physical models for material properties and improved trap models. By comparing with the performance of the well-utilized buried-gate incorporated with a field-plate (BG-FP) structure, it is shown that the proposed structure improves device properties in comprehensive aspects. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate–drain capacitance (Cgd) under a large drain voltage. A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less Cgd than a conventional FP. For microwave applications, 4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel. For high power applications, the proposed structure is able to endure higher operating voltage as well. The maximum saturation current density of 460 mA/mm is yielded. Also, the gate-lag ratio under a drain voltage of 20 V is close to 90%. In addition, 5% and 17.8% improvements in fT and fmax are obtained compared with a BG-FP MESFET in AC simulation, respectively. Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design.

  • Analytical drain current model for amorphous IGZO thin-film transistors in above-threshold regime

    He Hongyu, Zheng Xueren

    J. Semicond.  2011, 32(7): 074004

    doi: 10.1088/1674-4926/32/7/074004

    Abstract PDF Get Citation

    An analytical drain current model is presented for amorphous In–Ga–Zn–oxide thin-film transistors in the above-threshold regime, assuming an exponential trap states density within the bandgap. Using a charge sheet approximation, the trapped and free charge expressions are calculated, then the surface potential based drain current expression is developed. Moreover, threshold voltage based drain current expressions are presented using the Taylor expansion to the surface potential based drain current expression. The calculated results of the surface potential based and threshold voltage based drain current expressions are compared with experimental data and good agreements are achieved.

  • A novel lateral IGBT with a controlled anode for on-off-state loss trade-off improvement

    Chen Wensuo, Zhang Bo, Fang Jian, Li Zhaoji

    J. Semicond.  2011, 32(7): 074005

    doi: 10.1088/1674-4926/32/7/074005

    Abstract PDF Get Citation

    A new lateral insulated-gate bipolar transistor with a controlled anode (CA-LIGBT) on silicon-on-insulator (SOI) substrate is reported. Benefiting from both the enhanced conductivity modulation effect and the high resistance controlled electron extracting path, CA-LIGBT has a faster turn-off speed and lower forward drop, and the trade-off between off-state and on-state losses is better than that of state-of-the-art 3-D NCA-LIGBT, which we presented earlier. As the simulation results show, the ratios of figure of merit (FOM) for CA-LIGBT compared to that of 3-D NCA-LIGBT and conventional LIGBT are 1.45 : 1 and 59.53 : 1, respectively. And, the new devices can be created by using additional silicon direct bonding (SDB). So, from the power efficiency point of view, the proposed CA-LIGBT is a promising device for use in power ICs.

  • A new high voltage SOI LDMOS with triple RESURF structure

    Hu Xiarong, Zhang Bo, Luo Xiaorong, Yao Guoliang, Chen Xi, Li Zhaoji

    J. Semicond.  2011, 32(7): 074006

    doi: 10.1088/1674-4926/32/7/074006

    Abstract PDF Get Citation

    A novel triple RESURF (T-resurf) SOI LDMOS structure is proposed. This structure has a P-type buried layer. Firstly, the depletion layer can extend on both sides of the P-buried layer, serving as a triple RESURF and leading to a high drift doping and a low on-resistance. Secondly, at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side, which results in uniform bulk electric field distributions and an enhanced BV. The proposed structure is used in SOI devices for the first time. The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6 μm-thick SOI layer over a 2 μm-thick buried oxide layer, and its Rsp is reduced from 17.2 to 13.8 mΩcm2 in comparison with the double RESURF (D-resurf) SOI LDMOS. When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV2/Ron. It reduces Rsp by 29% in 400 V SOI LDMOS and by 38% in 550 V SOI LDMOS compared with the D-resurf structure.

  • Simulation study of new 3-terminal devices for high speed STT-RAM

    Zhang Shuchao, Hu Jiangfeng, Chen Peiyi, Deng Ning

    J. Semicond.  2011, 32(7): 074007

    doi: 10.1088/1674-4926/32/7/074007

    Abstract PDF Get Citation

    To improve the performance of spin transfer torque random access memory (STT-RAM), especially writing speed, we propose three modified 3-terminal STT-RAM cells. A magnetic dynamic process in the new structures was investigated through micro-magnetic simulation. The best switching speed of the new structures is 120% faster than that of the rectangular 3-terminal device. The optimized 3-terminal device offers high speed while maintaining the high reliability of the 3-terminal structure.

  • Fabrication of ZnO nanowall-network ultraviolet photodetector on Si substrates

    Su Shichen, Yang Xiaodong, Hu Candong

    J. Semicond.  2011, 32(7): 074008

    doi: 10.1088/1674-4926/32/7/074008

    Abstract PDF Get Citation

    ZnO nanowall networks were prepared by plasma-assisted molecular beam epitaxy without a catalyst on Si (111) substrates. The nanostructures have preferred orientation along the c axis. The nanostructures are about 10 to 20 nm thick and about 50 nm tall. The planar geometry photoconductive type metal–semiconductor–metal photodetector based on the ZnO nanowall networks exhibits a high and wide response spectrum, and no decrease from 250 to 360 nm. With the applied bias below 5 V, the dark current was below 6 μA, and the peak responsivity of 15 A/W was achieved at 360 nm. The UV (360 nm) to visible (450 nm) rejection ratio of around two orders could be extracted from the spectra response.

  • Sensitivity of MEMS microwave power sensor with the length of thermopile based on Fourier equivalent model

    Liu Tong, Liao Xiaoping, Wang Debo

    J. Semicond.  2011, 32(7): 074009

    doi: 10.1088/1674-4926/32/7/074009

    Abstract PDF Get Citation

    A Fourier equivalent model is introduced to research the thermal transfer behavior of a terminating-type MEMS microwave power sensor. The fabrication of this MEMS microwave power sensor is compatible with the GaAs MMIC process. Based on the Fourier equivalent model, the relationship between the sensitivity of a MEMS microwave power sensor and the length of thermopile is studied in particular. The power sensor is measured with an input power from 1 to 100 mW at 10 GHz, and the measurement results show that the power sensor has good input match characteristics and high linearity. The sensitivity calculated from a Fourier equivalent model is about 0.12, 0.20 and 0.29 mV/mW with the length at 40, 70 and 100 μm, respectively, while the sensitivity of the measurement results is about 0.10, 0.22 and 0.30 mV/mW, respectively, and the differences are below 0.02 mV/mW. The sensitivity expression based on the Fourier equivalent model is verified by the measurement results.

  • A novel structure of silicon-on-insulator microring biosensor based on Young's two-slit interference and its simulation

    Su Baoqing, Wang Chunxia, Kan Qiang, Li Junhua, Xie Yiyang, Wang Zhenzhen, Chen Hongda

    J. Semicond.  2011, 32(7): 074010

    doi: 10.1088/1674-4926/32/7/074010

    Abstract PDF Get Citation

    A novel silicon-on-insulator microring biosensor based on Young's twoslit interference has been demonstrated. The transducer signal from electric field intensity distribution on the interference screen is given by using the transfer matrix method (TMM) and two-slit interference principle. The result shows that the structure we propose is advantageous for sensing as the interference pattern is very sensitive to the ambient refractive index around the microring. A small perturbation in refractive index around the microring Δnc will result in a notable shift of destructive interference points (DIPs) on the interference screen. By detecting the shift of the DIPs, the ambient refractive index change can be obtained.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

    Zhao Yi, Wang Shenjie, Qin Yajie, Hong Zhiliang

    J. Semicond.  2011, 32(7): 075001

    doi: 10.1088/1674-4926/32/7/075001

    Abstract PDF Get Citation

    A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier (THA) in 0.13 μ m CMOS for an impulse radio ultra-wideband (IR-UWB) receiver is presented. The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency. This paper presents, to our knowledge for the second time, a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz. In this design, a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz. A resistive averaging technique is carefully analyzed to relieve noise aliasing. A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed, power consumption and noise aliasing. The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s. The core power of the ADC is 30 mW, excluding all of the buffers, and the active area is 0.6 mm2. The ADC achieves a figure of merit of 3.75 pJ/conversion-step.

  • A 50 MHz–1 GHz high linearity CATV amplifier with a 0.15 μm InGaAs PHEMT process

    Xu Jian, Wang Zhigong, Zhang Ying, Huang Jing

    J. Semicond.  2011, 32(7): 075002

    doi: 10.1088/1674-4926/32/7/075002

    Abstract PDF Get Citation

    A 50 MHz–1 GHz low noise and high linearity amplifier monolithic-microwave integrated-circuit (MMIC) for cable TV is presented. A shunt AC voltage negative feedback combined with source current negative feedback is adopted to extend the bandwidth and linearity. A novel DC bias feedback is introduced to stabilize the operation point, which improved the linearity further. The circuit was fabricated with a 0.15 μm InGaAs PHEMT (pseudomorphic high electron mobility transistor) process. The test was carried out in 75 Ω systems from 50 MHz to 1 GHz. The measurement results showed that it gave a small signal gain of 16.5 dB with little gain ripples of less than ±1 dB. An excellent noise figure of 1.7–2.9 dB is obtained in the designed band. The IIP3 is 16 dBm, which shows very good linearity. The CSO and CTB are high up to 68 dBc and 77 dBc, respectively. The chip area is 0.56 mm2 and the power dissipation is 110 mA with a 5 V supply. It is ideally suited to cable TV systems.

  • A wideband CMOS VGLNA based on single-to-differential stage and resistive attenuator for TV tuners

    Han Kefeng, Tan Xi, Tang Zhangwen, Min Hao

    J. Semicond.  2011, 32(7): 075003

    doi: 10.1088/1674-4926/32/7/075003

    Abstract PDF Get Citation

    A wideband CMOS variable gain low noise amplifier (VGLNA) based on a single-to-differential (S2D) stage and resistive attenuator is presented for TV tuner applications. Detailed analysis of input matching, noise figure (NF) and linearity for S2D is given. A highly linear passive resistive attenuator is proposed to provide 6 dB attenuation and input matching for each gain stage. The chip was fabricated by a 0.18 μm 1P6M CMOS process, and the measurements show that the VGLNA covers a gain range over 36.4 dB and achieves a maximum gain of 21.3 dB, a minimum NF of 3.0 dB, an IIP3 of 0.9 dBm and an IIP2 of 26.3 dBm at high gain mode with a power consumption less than 10 mA from a 1.8 V supply.

  • A low noise high efficiency buck DC–DC converter with sigma–delta modulation

    Cai Shujiang, Pi Changming, Yan Wei, Li Wenhong

    J. Semicond.  2011, 32(7): 075004

    doi: 10.1088/1674-4926/32/7/075004

    Abstract PDF Get Citation

    Some research efforts to improve the efficiency and noise performance of buck DC–DC converters are explored. A carefully designed power MOSFET driver, including a dead time controller, discontinuous current mode (DCM) controller and gate width controller, is proposed to improve efficiency. Instead of PWM modulation, sigma–delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike. The proposed converter has been designed and fabricated by a 0.35 μm CMOS process. Measured results show that the peak efficiency of the converter can reach 93% and sigma–delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.

  • A pseudo differential GmC complex filter with frequency tuning for IEEE802.15.4 applications

    Cheng Xin, Zhong Lungui, Yang Haigang, Liu Fei, Gao Tongqiang

    J. Semicond.  2011, 32(7): 075005

    doi: 10.1088/1674-4926/32/7/075005

    Abstract PDF Get Citation

    This paper presents a CMOS GmC complex filter for a low-IF receiver of the IEEE802.15.4 standard. A pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator. A detailed analysis of non-ideality of the OTA and the frequency tuning method is elaborated. The analysis and measurement results have shown that the center frequency of the complex filter could be tuned accurately. The chip was fabricated in a standard 0.35 μm CMOS process, with a single 3.3 V power supply. The filter consumes 2.1 mA current, has a measured in-band group delay ripple of less than 0.16 μs and an IRR larger than 28 dB at 2 MHz apart, which could meet the requirements of the IEEE802.15.4 standard.

  • Design of a total-dose radiation hardened monolithic CMOS DC–DC boost converter

    Liu Zhi, Ning Hongying, Yu Hongbo, Liu Youbao

    J. Semicond.  2011, 32(7): 075006

    doi: 10.1088/1674-4926/32/7/075006

    Abstract PDF Get Citation

    This paper presents the design and implementation of a monolithic CMOS DC–DC boost converter that is hardened for total dose radiation. In order to improve its radiation tolerant abilities, circuit-level and device-level RHBD (radiation-hardening by design) techniques were employed. Adaptive slope compensation was used to improve the inherent instability. The H-gate MOS transistors, annular gate MOS transistors and guard rings were applied to reduce the impact of total ionizing dose. A boost converter was fabricated by a standard commercial 0.35 μm CMOS process. The hardened design converter can work properly in a wide range of total dose radiation environments, with increasing total dose radiation. The efficiency is not as strongly affected by the total dose radiation and so does the leakage performance.

  • Design of a high performance CMOS charge pump for phase-locked loop synthesizers

    Li Zhiqun, Zheng Shuangshuang, Hou Ningbing

    J. Semicond.  2011, 32(7): 075007

    doi: 10.1088/1674-4926/32/7/075007

    Abstract PDF Get Citation

    A new high performance charge pump circuit is designed and realized in 0.18 μ m CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range. Furthermore, a method of adding a precharging current source is proposed to increase the initial charge current, which will speed up the settling time of CPPLLs. Test results show that the current mismatching can be less than 0.4% in the output voltage range of 0.4 to 1.7 V, with a charge pump current of 100 μ A and a precharging current of 70 μ A. The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

  • A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

    Li Zhenrong, Zhuang Yiqi, Li Bing, Jin Gang

    J. Semicond.  2011, 32(7): 075008

    doi: 10.1088/1674-4926/32/7/075008

    Abstract PDF Get Citation

    A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18 μ m CMOS technology. A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance. A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature (I/Q) local oscillating signal. A high-speed 8/9 dual-modulus prescaler (DMP), a programmable-delay phase frequency detector without dead-zone problem, and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz, and the phase noise is –98.53 dBc/Hz at 100-kHz offset and –121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply. The total area of the receiver is 2.4 × 1.6 mm2.

  • Reducing test-data volume and test-power simultaneously in LFSR reseeding-based compression environment

    Wang Weizheng, Kuang Jishun, You Zhiqiang, Liu Peng

    J. Semicond.  2011, 32(7): 075009

    doi: 10.1088/1674-4926/32/7/075009

    Abstract PDF Get Citation

    This paper presents a new test scheme based on scan block encoding in a linear feedback shift register (LFSR) reseeding-based compression environment. Meanwhile, our paper also introduces a novel algorithm of scan-block clustering. The main contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during scan shift and the number of specified bits that need to be generated via LFSR reseeding. Thus, it can significantly reduce the test power and test data volume. Experimental results using Mintest test set on the larger ISCAS’89 benchmarks show that the proposed method reduces the switching activity significantly by 72%–94% and provides a best possible test compression of 74%–94% with little hardware overhead.

  • On modeling the digital gate delay under process variation

    Gao Mingzhi, Ye Zuochang, Wang Yan, Yu Zhiping

    J. Semicond.  2011, 32(7): 075010

    doi: 10.1088/1674-4926/32/7/075010

    Abstract PDF Get Citation

    To achieve a characterization method for the gate delay library used in block based statistical static timing analysis with neither unacceptably poor accuracy nor forbiddingly high cost, we found that general-purpose gate delay models are useful as intermediaries between the circuit simulation data and the gate delay models in required forms. In this work, two gate delay models for process variation considering different driving and loading conditions are proposed. From the testing results, these two models, especially the one that combines effective dimension reduction (EDR) from statistics society with comprehensive gate delay models, offer good accuracy with low characterization cost, and they are thus competent for use in statistical timing analysis (SSTA). In addition, these two models have their own value in other SSTA techniques.

  • A novel high reliability CMOS SRAM cell

    Xie Chengmin, Wang Zhongfang, Wu Longsheng, Liu Youbao

    J. Semicond.  2011, 32(7): 075011

    doi: 10.1088/1674-4926/32/7/075011

    Abstract PDF Get Citation

    A novel 8T single-event-upset (SEU) hardened and high static noise margin (SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor, the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell. So the hold, read SNM and critical charge increase greatly. The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors. The hold and read SNM of the new cell increase by 72% and 141.7%, respectively, compared to the 6T design, but it has a 54% area overhead and read performance penalty. According to these features, this novel cell suits high reliability applications, such as aerospace and military.

  • A radiation-hardened SOI-based FPGA

    Han Xiaowei, Wu Lihua, Zhao Yan, Li Yan, Zhang Qianli, Chen Liang, Zhang Guoquan, Li Jianzhong, Yang Bo, Gao Jiantou, Wang Jian, Li Ming, Liu Guizhai, Zhang Feng, Guo Xufeng, Stanley L. Chen, Liu Zhongli, Yu Fang, Zhao Kai

    J. Semicond.  2011, 32(7): 075012

    doi: 10.1088/1674-4926/32/7/075012

    Abstract PDF Get Citation

    A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT. The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 × 1011 rad(Si)/s and a neutron fluence immunity of 1 × 1014 n/cm2.

  • A process-insensitive thermal protection circuit

    Zhao Lei, Zhang Haiying, Huang Shuilong, Wang Xiaosong

    J. Semicond.  2011, 32(7): 075013

    doi: 10.1088/1674-4926/32/7/075013

    Abstract PDF Get Citation

    A novel process-insensitive thermal protection structure has been developed. This circuit contains several sub-circuits such as band-gap reference, reference output buffer, resistance voltage divider branch, and hysteresis circuit. By using reference buffer, the precise reference voltage from band-gap reference is delivered to resistance voltage divider branch and is divided precisely. Then the threshold temperatures of this protection circuit can be set by this precise voltage, unaffected by process variation and mismatch. A hysteresis circuit is also used here to prevent thermal oscillation. This circuit is fabricated in TSMC 0.18 μm CMOS technology, and occupies about 3 × 104 μm2 chip area.

  • SEMICONDUCTOR TECHNOLOGY

  • Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal–oxide–semiconductor devices

    Li Yongliang, Xu Qiuxia

    J. Semicond.  2011, 32(7): 076001

    doi: 10.1088/1674-4926/32/7/076001

    Abstract PDF Get Citation

    A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal–oxide–semiconductor (CMOS) devices is investigated. Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile. First, a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate. Then different BCl3-based plasmas are applied to etch the TaN metal gate and find that BCl3/Cl2/O2/Ar plasma is a suitable choice to get a vertical TaN profile. Moreover, considering that Cl2 almost has no selectivity to Si substrate, BCl3/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl3/Cl2/O2/Ar plasma. Finally, we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.

  • Effect of alkaline slurry on the electric character of the pattern Cu wafer

    Hu Yi, Liu Yuling, Liu Xiaoyan, He Yangang, Wang Liran, Zhang Baoguo

    J. Semicond.  2011, 32(7): 076002

    doi: 10.1088/1674-4926/32/7/076002

    Abstract PDF Get Citation

    For process integration considerations, we will investigate the impact of chemical mechanical polishing (CMP) on the electrical characteristics of the pattern Cu wafer. In this paper, we investigate the impacts of the CMP process with two kinds of slurry, one of which is acid slurry of SVTC and the other is FA/O alkaline slurry purchased from Tianjin Jingling Microelectronic Material Limited. Three aspects were investigated: resistance, capacitance and leakage current. The result shows that after polishing by the slurry of FA/O, the resistance is lower than the SVTC. After polishing by the acid slurry and FA/O alkaline slurry, the difference in capacitance is not very large. The values are 0.1 nF and 0.12 nF, respectively. The leakage current of the film polished by the slurry of FA/O is 0.01 nA, which is lower than the slurry of SVTC. The results show that the slurry of FA/O produced less dishing and oxide loss than the slurry of SVTC.

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