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Volume 32, Issue 2, Feb 2011

SEMICONDUCTOR PHYSICS

• Spin transport properties in double quantum rings connected in series

J. Semicond.  2011, 32(2): 022001

doi: 10.1088/1674-4926/32/2/022001

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A new model of metal/semiconductor/metal double-quantum-ring connected in series is proposed and the transport properties in this model are theoretically studied. The results imply that the transmission coefficient shows periodic variations with increasing semiconductor ring size. The effects of the magnetic field and Rashba spin-orbit interaction on the transmission coefficient for two kinds of spin state electrons are different. The number of the transmission coefficient peaks is related to the length ratio between the upper arm and the half circumference of the ring£®In addition, the transmission coefficient shows oscillation behavior with enhanced external magnetic field, and the corresponding average value is related to the two leads' relative position£®

• The impact of [110]/(001) uniaxial stress on the valence band structure and hole effective mass of silicon

J. Semicond.  2011, 32(2): 022002

doi: 10.1088/1674-4926/32/2/022002

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The valence band structure and hole effective mass of silicon under a uniaxial stress in surface along the direction was detailed investigated in the framework of theory. The results demonstrated that£ºthe splitting energy between the top band and the second band for uniaxial compressive stress is bigger than that of the tensile one at the same stress magnitude, and of all common used crystallographic direction, such as , , and , the effective mass for the top band along crystallographic direction is lower under uniaxial compressive stress compared with other stresses and crystallographic directions configurations. In view of suppressing the scattering and reducing the effective mass, the crystallographic direction is most favorable to be used as transport direction of the charge carrier to enhancement mobility when a uniaxial compressive stress along direction is applied. The obtained results can provide a theory reference for the design and the selective of optimum stress and crystallorgraphic direction configuration of uniaxial strained silicon devices.

• Structural and optical properties of Cd0.8Zn0.2S thin films

J. Semicond.  2011, 32(2): 022003

doi: 10.1088/1674-4926/32/2/022003

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Cd1-xZnxS thin films were deposited on glass substrates by a vacuum coevaporation method. The structural, compositional, and optical properties of as-deposited Cd0.8Zn0.2S films were investigated using X-ray diffraction (XRD), X-ray fluorescence (XRF), X-ray photoelectron spectroscopy (XPS), and optical transmittance spectrum. The thin films are hexagonal in structure, with strong preferential orientation along the (002) planes. The composition of Cd1-xZnxS thin films monitored by a quartz crystal oscillator agrees well with that obtained from XRF and XPS measurements. The optical constants, such as refractive index, single-oscillator energy, dispersion energy, absorption coefficients, and the optical band gap, were deduced by the Swanepoel's method, in combination with the Wemple and DiDomenico single-oscillator model, from the transmission spectrum of Cd0.8Zn0.2S thin films.

• SEMICONDUCTOR MATERIALS

• Structural and optical properties of polycrystalline CdS thin films depositedby electron beam evaporation

J. Semicond.  2011, 32(2): 023001

doi: 10.1088/1674-4926/32/2/023001

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Highly crystalline and transparent cadmium sulphide (CdS) films were deposited on glass substrate by electron beam evaporation technique. The structural and optical properties of the films were investigated. The X-ray diffraction analysis revealed that the CdS films have a hexagonal structure and exhibit preferred orientation along the (002) plane. Meanwhile, the crystalline quality of samples increased first and then decreased as the substrate temperature improved, which is attributed to the variation in film thickness. UV-vis spectra of CdS films indicate that the absorption edge becomes steeper and the band gap present fluctuation changes in the range of 2.389--2.448 eV as the substrate temperature increased. The photoluminescence peak of the CdS films was found to be broadened seriously and there only emerges a red emission band at 1.60 eV. The above results were analyzed and discussed.

• Growth of SiO2 nanowires on different substrates using Au as a catalyst

J. Semicond.  2011, 32(2): 023002

doi: 10.1088/1674-4926/32/2/023002

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SiO2 nanowires were prepared on a SiO2/Si(111) or Si substrate using Au as a catalyst. The products were characterized using scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). SEM shows that large amounts of SiO2 nanowires with a diameter of 20--150 nm and length of several nanometers were formed on the entire surface of the substrate. XPS analysis indicates that the nanowires have the composition of Si and O in an atomic ratio of about 1 : 2, and their composition approximates that of SiO2. The formation of the SiO2 nanowires was controlled by the vapor-liquid-solid mechanism. It is found that the annealing time affects the morphology of the products. Finally, the effect of the substrates on the growth of SiO2 nanowires was discussed. The Si source of the SiO2 nanowires comes from the substrate or Si powder for different substrates.

• SEMICONDUCTOR DEVICES

• Forward gated-diode method for parameter extraction of MOSFETs

J. Semicond.  2011, 32(2): 024001

doi: 10.1088/1674-4926/32/2/024001

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The forward gated-diode method is used to extract the dielectric oxide thickness and body doping concentration of MOSFETs, especially when both of the variables are unknown previously. First, the dielectric oxide thickness and the body doping concentration as a function of forward gated-diode peak recombination--generation (R--G) current are derived from the device physics. Then the peak R--G current characteristics of the MOSFETs with different dielectric oxide thicknesses and body doping concentrations are simulated with ISE-Dessis for parameter extraction. The results from the simulation data demonstrate excellent agreement with those extracted from the forward gated-diode method.

• Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage

J. Semicond.  2011, 32(2): 024002

doi: 10.1088/1674-4926/32/2/024002

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The lateral super junction (SJ) power devices suffer the substrate-assisted depletion (SAD) effect, which breaks the charge balance of SJ resulting in the low breakdown voltage (BV). A solution based on enhancing the electric field of the dielectric buried layer is investigated for improving the BV of super junction LDMOSFET (SJ-LDMOS). High density interface charges enhance the electric field in the buried oxide (BOX) layer to increase the block voltage of BOX, which suppresses the SAD effect to achieve the charge balance of SJ. In order to obtain the linear enhancement of electric field, SOI SJ-LDMOS with trenched BOX is presented. Because the trenched BOX self-adaptively collects holes according to the variable electric field strength, the approximate linear charge distribution is formed on the surface of the BOX to enhance the electric field according to the need. As a result, the charge balance between N and P pillars of SJ is achieved, which improves the BV of SJ-LDMOS to close that of the idea SJ structure.

• Body-contact self-bias effect in partially depleted SOI-CMOS and alternatives to suppress floating body effect

J. Semicond.  2011, 32(2): 024003

doi: 10.1088/1674-4926/32/2/024003

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As SOI-CMOS technology nodes reach the tens of nanometer regime, body-contacts become more and more ineffective to suppress the floating body effect. In this paper, self-bias effect as the cause for this failure is analyzed and discussed in depth with respect to different structures and conditions. Other alternative approaches to suppressing the floating body effect are also introduced and discussed.

• Improved Nonlinear Model of HEMTs with Independent Transconductance Tail-Off Fitting

J. Semicond.  2011, 32(2): 024004

doi: 10.1088/1674-4926/32/2/024004

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In this paper, we present an improved large-signal device model of GaAs/ GaN HEMTs, amenable for use in the commercial nonlinear simulators. The proposed model includes a new exponential function to independently control the transconductance (Gm) compression/ tail-off behaviors. And the main advantage of this model is to provide a simple and coherent description of the bias-dependent drain current (I-V) that is valid in all regions of operation. All the aspects of the model are validated for 0.25-¦Ìm gate-lengths GaAs and GaN HEMT processes. The simulation results of DC/ Pulsed I-V, RF large-signal power and intermodulation distortion (IMD) products show an excellent agreement with the measured data.

• A novel structure in reducing the on-resistance of a VDMOS

J. Semicond.  2011, 32(2): 024005

doi: 10.1088/1674-4926/32/2/024005

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A novel structure of a VDMOS in reducing on-resistance is proposed. With this structure, the specific on-resistance value of the VDMOS is reduced by 22% of that of the traditional VDMOS structure as the breakdown voltage maintained the same value in theory, and there is only one additional mask in processing the new structure VDMOS, which is easily fabricated. With the TCAD tool, one 200 V N-channel VDMOS with the new structure is analyzed, and simulated results show that a specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in the strip-gate VDMOS area.

• A low voltage and small hysteresis C60 thin film transistor

J. Semicond.  2011, 32(2): 024006

doi: 10.1088/1674-4926/32/2/024006

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Organic thin film transistors with C60 as an n-type semiconductor have been fabricated. A tantalum pentoxide (Ta2O5)/poly-methylmethacrylate (PMMA) double-layer structured gate dielectric was used. The Ta2O5 layer was prepared by using a simple solution-based and economical anodization technique. Our results demonstrate that double gate insulators can combine the advantage of Ta2O5 with high dielectric constant and polymer insulator for a better interface with the organic semiconductor. The performance of the device can be improved obviously with double gate insulators, compared to that obtained by using a single Ta2O5 or PMMA insulator. Then, a good performance n-type OTFT, which can work at 10 V with mobility, threshold voltage and on/off current ratio of, respectively, 0.26 cm2/(V.s), 3.2 V and 8.31 ¡Á 104 , was obtained. Moreover, such an OTFT shows a negligible hysteresis effect'' contributing to the hydroxyl-free insulator surface.

• A new shallow trench and planar gate MOSFET structure based on VDMOS technology

J. Semicond.  2011, 32(2): 024007

doi: 10.1088/1674-4926/32/2/024007

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This paper proposes a new shallow trench and planar gate MOSFET (TPMOS) structure based on VDMOS technology, in which the shallow trench is located at the center of the n- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.

• A thick SOI UVLD LIGBT on partial membrane

J. Semicond.  2011, 32(2): 024008

doi: 10.1088/1674-4926/32/2/024008

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A thick SOI LIGBT structure with a combination of uniform and variation in lateral doping profiles (UVLD) on partial membrane (UVLD PM LIGBT) is proposed. The silicon substrate under the drift region is selectively etched to remove the charge beneath the buried oxide so that the potential lines can release below the membrane, resulting in an enhanced breakdown voltage. Moreover, the thick SOI LIGBT with the advantage of a large current flowing and a thermal diffusing area achieves a strong current carrying capability and a low junction temperature. The current carrying capability (VAnode = 6 V, VGate = 15 V) increases by 16% and the maximal junction temperature (1 mW/¦Ìm) decreases by 30 K in comparison with that of a conventional thin SOI structure.

• Electrical characteristics of a vertical light emitting diode with n-type contacts on a selectively wet-etching roughened surface

J. Semicond.  2011, 32(2): 024009

doi: 10.1088/1674-4926/32/2/024009

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Low resistance and thermally stable n-type contacts to N-polar GaN are essentially important for vertical light emitting diodes (VLEDs). The electrical characteristics of VLEDs with n-type contacts on a roughened and flat N-polar surface have been compared. VLEDs with contacts deposited on a roughened surface exhibit lower leakage currents yet a higher operating voltage. Based on this, a new scheme by depositing metallization contacts on a selectively wet-etching roughened surface has been developed. Excellent electrical and optical characteristics have been achieved with this method. An aging test further confirmed its stability.

• 16 channel 200 GHz arrayed waveguide grating based on Si nanowire waveguides

J. Semicond.  2011, 32(2): 024010

doi: 10.1088/1674-4926/32/2/024010

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A 16 channel arrayed waveguide grating demultiplexer with 200 GHz channel spacing based on Si nanowire waveguides is designed. The transmission spectra response simulated by transmission function method shows that the device has channel spacing of 1.6 nm and crosstalk of 31 dB. The device is fabricated by 193 nm deep UV lithography in silicon-on-substrate. The demultiplexing characteristics are observed with crosstalk of 5--8 dB, central channel's insertion loss of 2.2 dB, free spectral range of 24.7 nm and average channel spacing of 1.475 nm. The cause of the spectral distortion is analyzed specifically.

• Comparison of the copper and gold wire bonding processes for LED packaging

J. Semicond.  2011, 32(2): 024011

doi: 10.1088/1674-4926/32/2/024011

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Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame. The gold wire bonding process has been widely used in LED packaging industry currently. However, due to the high cost of gold wire, copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving. In this paper, the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation. This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.

• SEMICONDUCTOR INTEGRATED CIRCUITS

• A 100-MHz bandpass sigma--delta modulator with a 75-dB dynamic range for IF receivers

J. Semicond.  2011, 32(2): 025001

doi: 10.1088/1674-4926/32/2/025001

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A fourth-order switched-capacitor bandpass ¦² ¦¤ modulator is presented for digital intermediate-frequency (IF) receivers. The circuit operates at a sampling frequency of 100 MHz. The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators. The modulator is implemented in a 0.13-¦Ìm standard CMOS process. The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB, respectively, over a bandwidth of 200 kHz centered at 25 MHz, and the power dissipation is 8.2 mW at a 1.2 V supply.

• A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

J. Semicond.  2011, 32(2): 025002

doi: 10.1088/1674-4926/32/2/025002

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An analog/digital reconfigurable automatic gain control (AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What's more, a novel DC offset cancellation (DCOC) circuit with an HPCF (high pass cutoff frequency) less than 10 kHz is proposed. The AGC is fabricated by a 0.18 ¦Ìm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ¡Á 300 ¦Ìm2.

• A baseband LPF for GSM, TD-SCDMA and WCDMA multi-mode transmitters

J. Semicond.  2011, 32(2): 025003

doi: 10.1088/1674-4926/32/2/025003

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This paper describes a low-pass reconfigurable baseband filter for GSM, TD-SCDMA and WCDMA multi-mode transmitters. To comply with 3GPP emission mask and limit TX leakage at the RX band, the out-of-band noise performance is optimized. Due to the distortion caused by the subthreshold leakage current of the switches used in capacitor array, a capacitor bypass technique is proposed to improve the filter's linearity. An automatic frequency tuning circuit is adopted to compensate the cut-off frequency variation. Simulation results show that the filter achieves an in-band input-referred third-order intercept point (IIP3) of 47 dBm at 1.2-V power supply and the out-of-band noise can meet TX SAW-less requirement for WCDMA & TD-SCDMA. The baseband filter incorporates --40 to 0 dB programmable gain control that is accurately variable in 0.5 dB steps. The filter's cut-off frequency can be reconfigured for GSM/TD-SCDMA/WCDMA multi-mode transmitter. The implemented baseband filter draws 3.6 mA from a 1.2-V supply in a 0.13 ¦Ìm CMOS process.

• A CMOS variable gain LNA for UWB receivers

J. Semicond.  2011, 32(2): 025004

doi: 10.1088/1674-4926/32/2/025004

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A CMOS variable gain low noise amplifier (LNA) is presented for 4.2--4.8 GHz ultra-wideband application in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13-¦Ìm RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S(1,1) less than --9 dB and S(2,2) less than --10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is --10 dBm and input third order intercept point (IIP3) is --2 dBm.

• A low-power triple-mode sigma--delta DAC for reconfigurable (WCDMA/TD-SCDMA/GSM) transmitters

J. Semicond.  2011, 32(2): 025005

doi: 10.1088/1674-4926/32/2/025005

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A sigma--delta (¦² ¦¤) DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio (SDR) system is presented. The conversion frequency, transfer function of the digital filter and the ¦² ¦¤ modulator, word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA, TD-SCDMA and GSM standards. The ¦² ¦¤ DAC fabricated in SMIC 0.13-¦Ìm CMOS process occupies a die area of 0.72 mm2, while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage. The measured SFDR is 62.8/60.1/75.5 dB for WCDMA/TD-SCDMA/GSM mode, respectively.

• A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC

J. Semicond.  2011, 32(2): 025006

doi: 10.1088/1674-4926/32/2/025006

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A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-¦Ìm CMOS. An opamp-sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB (ENOB = 9.69 bits) and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.

• Low power mapping for AND/XOR circuits and its application in searching the best mixed-polarity

J. Semicond.  2011, 32(2): 025007

doi: 10.1088/1674-4926/32/2/025007

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A low power mapping algorithm for technology independent AND/XOR circuits is proposed. In this algorithm, the average power of the static mixed-polarity Reed--Muller (MPRM) circuits is minimized by generating a two-input gates circuit to optimize the switching active of nodes, and the power and area of MPRM circuits are estimated by using gates from a given library. On the basis of obtaining an optimal power MPRM circuit, the best mixed-polarity is found by combining an exhaustive searching method with polarity conversion algorithms. Our experiments over 18 benchmark circuits show that compared to the power optimization for fixed-polarity Reed--Muller circuits and AND/OR circuits, power saving is up to 44.22% and 60.09%, and area saving is up to 14.13% and 32.72%, respectively.

• A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction

J. Semicond.  2011, 32(2): 025008

doi: 10.1088/1674-4926/32/2/025008

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A low power 10-bit 250-k sample per second (KSPS) cyclic analog to digital converter (ADC) is presented. The ADC's offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator's offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 ¦Ìm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 ¡Á 0.68 mm2.

• A differential low-voltage high gain current-mode integrated RF receiver front-end

J. Semicond.  2011, 32(2): 025009

doi: 10.1088/1674-4926/32/2/025009

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A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (Gm-LNA) and a differential current-mode down converted mixer. The single terminal of the Gm-LNA contains just one MOS transistor, two capacitors and two inductors. The gate--source shunt capacitors, Cx1 and Cx2, can not only reduce the effects of gate--source Cgs on resonance frequency and input-matching impedance, but they also enable the gate inductance Lg1,2 to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 ¦Ìm CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of --7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.

• A 1.0 V differential VCO in 0.13 ¦Ìm CMOS technology

J. Semicond.  2011, 32(2): 025010

doi: 10.1088/1674-4926/32/2/025010

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A differential complementary LC voltage controlled oscillator (VCO) with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS (I-MOS) capacitors and an on-chip inductor. The resonator Q factor is mainly limited by the on-chip inductor. It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz. The proposed VCO is implemented in the SMIC 0.13 ¦Ìm 1P8M MMRF CMOS process, and the chip area is 1.0 ¡Á 0.8 mm2. The free-running frequency is from 5.73 to 6.35 GHz. When oscillating at 6.35 GHz, the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is --120.14 dBc/Hz. The figure of merit of the proposed VCO is --192.13 dBc/Hz.

• A wideband low power low phase noise dual-modulus prescaler

J. Semicond.  2011, 32(2): 025011

doi: 10.1088/1674-4926/32/2/025011

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This paper describes a novel divide-by-32/33 dual-modulus prescaler (DMP). Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18-¦Ìm CMOS process of SMIC. The measured results show that the DMP's operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is --134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57 ¡Á 30 ¦Ìm2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications.

• Reset noise reduction through column-level feedback reset in CMOS image sensors

J. Semicond.  2011, 32(2): 025012

doi: 10.1088/1674-4926/32/2/025012

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A low reset noise CMOS image sensor (CIS) based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18 ¦Ìm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6 ¦Ìs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination.

• SEMICONDUCTOR TECHNOLOGY

• Novel photoresist stripping technology using steam-water mixture

J. Semicond.  2011, 32(2): 026001

doi: 10.1088/1674-4926/32/2/026001

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A novel wet vapor photoresist stripping technology is developed as an alternative to dry plasma ashing and wet stripping. Experiments using this technology to strip hard baked SU-8 photoresist, aurum and chromium film are carried out. Then the images of stripping results are shown and the mechanism is analyzed and discussed. The most striking result of this experiment is that the spraying mixture of steam and water droplets can strip photoresist and even metal film with ease.