Issue Browser

Volume 32, Issue 11, Nov 2011


  • Local charge neutrality condition, Fermi level and majority carrier density of a semiconductor with multiple localized multi-level intrinsic/impurity defects

    Ken K. Chin

    J. Semicond.  2011, 32(11): 112001

    doi: 10.1088/1674-4926/32/11/112001

    Abstract PDF Get Citation

    For semiconductors with localized intrinsic/impurity defects, intentionally doped or unintentionally incorporated, that have multiple transition energy levels among charge states, the general formulation of the local charge neutrality condition is given for the determination of the Fermi level and the majority carrier density. A graphical method is used to illustrate the solution of the problem. Relations among the transition energy levels of the multi-level defect are derived using the graphical method. Numerical examples are given for p-doping of the CdTe thin film used in solar panels and semi-insulating Si to illustrate the relevance and importance of the issues discussed in this work.

  • Property comparison of polarons in zinc-blende and wurtzite GaN/AlN quantum wells

    Zhu Jun, Ban Shiliang, Ha Sihua

    J. Semicond.  2011, 32(11): 112002

    doi: 10.1088/1674-4926/32/11/112002

    Abstract PDF Get Citation

    The properties of polarons in zinc-blende and wurtzite GaN/AlN quantum wells with Fröhlich interaction Hamiltonians are compared in detail. The energy shifts of polarons at ground state due to the interface (IF), confined (CO) and half-space phonon modes are calculated by a finite-difference computation combined with a modified LLP variational method. It is found that the two Fröhlich interaction Hamiltonians are consistent with each other when the anisotropic effect from the z-direction and the x-y plane is neglected. The influence of the anisotropy on the polaron energy shifts due to the IF phonon modes for a smaller well width or due to the CO phonon modes for a moderate well width is obvious. In addition, the built-in electric field has a remarkable effect on the polaron energy shifts contributed by the various phonon modes.

  • AlGaAs/GaAs tunnel junctions in a 4-J tandem solar cell

    Lü Siyu, Qu Xiaosheng

    J. Semicond.  2011, 32(11): 112003

    doi: 10.1088/1674-4926/32/11/112003

    Abstract PDF Get Citation

    The III-V compound tandem solar cell is a third-generation new style solar cell with ultra-high efficiency. The energy band gaps of the sub-cells in a GaInP/GaAs/InGaAs/Ge 4-J tandem solar cell are 1.8, 1.4, 1.0 and 0.7 eV, respectively. In order to match the currents between sub-cells, tunnel junctions are used to connect the sub-cells. The characteristics of the tunnel junction, the material used in the tunnel junction, the compensation of the tunnel junction to the overall cell's characteristics, the tunnel junction's influence on the current density of sub-cells and the efficiency increase are discussed in the paper. An AlGaAs/GaAs tunnel junction is selected to simulate the cell's overall characteristics by PC1D, current densities of 16.02, 17.12, 17.75 and 17.45 mA/cm2 are observed, with a Voc of 3.246 V, the energy conversion efficiency under AM0 is 33.9%.

  • As2S8 planar waveguide: refractive index changes following an annealing and irradiation and annealing cycle, and light propagation features

    Zou Liner, Wang Gouri, Shen Yun, Chen Baoxue, Mamoru Iso

    J. Semicond.  2011, 32(11): 112004

    doi: 10.1088/1674-4926/32/11/112004

    Abstract PDF Get Citation

    The refractive index of as-evaporated amorphous semiconductor As2S8 film upon an annealing and saturation irradiation and annealing cycle is reversible. Upon successive treatment with annealing and non-saturation irradiation and further annealing, the refractive index of the as-evaporated amorphous semiconductor As2S8 film reaches a maximum value and then its reversibility occurs upon annealing. The annealing of the amorphous semiconductor As2S8 films results in the stabilization of the structure through changes of the S-S bonds in the nearest environment, accompanied by a decrease of film thickness. The As2S8 planar waveguide after annealing (130 ℃) and saturation irradiation and annealing (130 ℃) shows a good propagation characteristic with ca. 0.27 dB/cm low propagation loss of the 632.8 nm guided mode.


  • Potential of asymmetrical Si/Ge and Ge/Si based hetero-junction transit time devices over homo-junction counterparts for generation of high power

    Moumita Mukherjee, Pravash R. Tripathy, S. P. Pati

    J. Semicond.  2011, 32(11): 113001

    doi: 10.1088/1674-4926/32/11/113001

    Abstract PDF Get Citation

    Static and dynamic properties of both complementary n-Ge/p-Si and p-Ge/n-Si hetero-junction Double-Drift IMPATT diodes have been investigated by an advanced and realistic computer simulation technique, developed by the authors, for operation in the Ka-, V- and W-band frequencies. The results are further compared with corresponding Si and Ge homo-junction devices. The study shows high values of device efficiency, such as 23%, 22% and 21.5%, for n-Ge/p-Si IMPATTs at the Ka, V and W bands, respectively. The peak device negative conductances for n-Si/p-Ge and n-Ge/p-Si hetero-junction devices found to be 50.7 ? 106 S/m2 and 71.3 ? 106 S/m2, which are ~3-4 times better than their Si and Ge counterparts at the V-band. The computed values of RF power-density for n-Ge/p-Si hetero-junction IMPATTs are 1.0 ? 109, 1.1 ? 109 and 1.4 ? 109 W/m2, respectively, for Ka-, V- and W-band operation, which can be observed to be the highest when compared with Si, Ge and n-Si/p-Ge devices. Both of the hetero-junctions, especially the n-Ge/p-Si hetero-junction diode, can thus become a superior RF-power generator over a wide range of frequencies. The present study will help the device engineers to choose a suitable material pair for the development of high-power MM-wave IMPATT for applications in the civil and defense-related arena.

  • Effect of deposition conditions on the physical properties of SnxSy thin films prepared by the spray pyrolysis technique

    M. R. Fadavieslam, N. Shahtahmasebi, M. Rezaee-Roknabadi, M. M. Bagheri-Mohagheghi

    J. Semicond.  2011, 32(11): 113002

    doi: 10.1088/1674-4926/32/11/113002

    Abstract PDF Get Citation

    Tin sulfide thin films (SnxSy) with an atomic ratio of y/x = 0.5 have been deposited on a glass substrate by spray pyrolysis. The effects of deposition parameters, such as spray solution rate (R), substrate temperature (Ts) and film thickness (t), on the structural, optical, thermo-electrical and photoconductivity related properties of the films have been studied. The precursor solution was prepared by dissolving tin chloride (SnCl4, 5H2O) and thiourea in propanol, and SnxSy thin film was prepared with a mole ratio of y/x = 0.5. The prepared films were characterized by X-ray diffraction (XRD), scanning electron microscopy (SEM) and UV-vis spectroscopy. It is indicated that the XRD patterns of SnxSx films have amorphous and polycrystalline structures and the size of the grains has been changed from 7 to 16 nm. The optical gap of SnxSx thin films is determined to be about 2.41 to 3.08 eV by a plot of the variation of (αhν)2 versus related to the change of deposition conditions. The thermoelectric and photo-conductivity measurement results for the films show that these properties are depend considerably on the deposition parameters.

  • Raman analysis of epitaxial graphene on 6H-SiC (000-1) substrates under low pressure environment

    Wang Dangchao, Zhang Yuming, Zhang Yimen, Lei Tianmin, Guo Hui, Wang Yuehu, Tang Xiaoyan, Wang Hang

    J. Semicond.  2011, 32(11): 113003

    doi: 10.1088/1674-4926/32/11/113003

    Abstract PDF Get Citation

    This article investigates the formation mechanism of epitaxial graphene on 6H-SiC (0001) substrates under low pressure of \,2 mbar environment. It is shown that the growth temperature dramatically affects the formation and quality of epitaxial graphene. The higher growing temperature is of great benefit to the quality of epitaxial graphene and also can reduce the impact of the substrate for graphene. By analyzing Raman data, we conclude that epitaxial graphene grown at 1600 ℃ has a turbostratic graphite structure. The test from scanning electron microscopy (SEM) indicates that the epitaxial graphene has a size of 10 μm. This research will provide a feasible route for fabricating larger size of epitaxial graphene on SiC substrate.


  • GIDL current degradation in LDD nMOSFET under hot hole stress

    Chen Haifeng, Ma Xiaohua, Guo Lixin, Du Huimin

    J. Semicond.  2011, 32(11): 114001

    doi: 10.1088/1674-4926/32/11/114001

    Abstract PDF Get Citation

    The degradation of gate-induced drain leakage (GIDL) current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter IDIFF. IDIFF is the difference of GIDL currents measured under two conditions of drain voltage VD = 1.4 V and gate voltage VG = -1.4 V while VDG is fixed. After the stress GIDL currents decay due to holes trapping in the oxide around the gate-to-drain overlap region. These trapped holes diminish ΔEX which is the deference of the lateral electrical field of these two symmetrical measurement conditions in the overlap region so as to make IDIFF lessening. IDIFF extracted from GIDL currents decreases with increasing stress time t. The degradation shifts of IDIFF,MAXIDIFF,MAX) follows a power law against t: ΔIDIFF,MAXtm, m = 0.3. Hot electron stress is performed to validate the related mechanism.

  • Design of 700 V triple RESURF nLDMOS with low on-resistance

    Yin Shan, Qiao Ming, Zhang Yongman, Zhang Bo

    J. Semicond.  2011, 32(11): 114002

    doi: 10.1088/1674-4926/32/11/114002

    Abstract PDF Get Citation

    A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ·cm2 is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.

  • A novel high voltage LIGBT with an n-region in p-substrate

    Cheng Jianbing, Zhang Bo, Li Zhaoji

    J. Semicond.  2011, 32(11): 114003

    doi: 10.1088/1674-4926/32/11/114003

    Abstract PDF Get Citation

    A novel 4 μm thickness drift region lateral insulated gate bipolar transistor with a floating n-region (NR-LIGBT) in p-substrate is proposed. Due to the field modulation from the n-region, the vertical blocking capability is enhanced and the breakdown voltage is improved significantly. Low area cost, high current capability and short turn-off time are achieved because of the high average electric field per micron. Simulation results show that the blocking capability of the new LIGBT increases by about 58% when compared with the conventional LIGBT (C-LIGBT) for the same 100 μm drift region length. Furthermore, the turn-off time is shorter than that of the conventional LIGBT for nearly same blocking capability.

  • Analytical model for the dispersion of sub-threshold current in organic thin-film transistors

    Chen Yingping, Shang Liwei, Ji Zhuoyu, Wang Hong, Han Maixing, Liu Xin, Liu Ming

    J. Semicond.  2011, 32(11): 114004

    doi: 10.1088/1674-4926/32/11/114004

    Abstract PDF Get Citation

    This paper proposes an equivalent circuit model to analyze the reason for the dispersion of sub-threshold current (also known as zero-current point dispersion) in organic thin-film transistors. Based on the level 61 amorphous silicon thin-film transistor model in star-HSPICE, the results from our equivalent circuit model simulation reveal that zero-current point dispersion can be attributed to two factors: large contact resistance and small gate resistance. Furthermore, it is found that decreasing the contact resistance and increasing the gate resistance can efficiently reduce the dispersion. If the contact resistance can be controlled to 0 Ω, all the zero-current points can gather together at the base point. A large gate resistance is good for constraining the dispersion of the zero-current points and gate leakage. The variances of the zero-current points are 0.0057 and nearly 0 when the gate resistances are 17 MΩ and 276 MΩ, respectively.

  • Improvement on the dynamical performance of a power bipolar static induction transistor with a buried gate structure

    Wang Yongshun, Feng Jingjing, Liu Chunjuan, Wang Zaixing, Zhang Caizhen, Chang Peng

    J. Semicond.  2011, 32(11): 114005

    doi: 10.1088/1674-4926/32/11/114005

    Abstract PDF Get Citation

    The failure of a bipolar static induction transistor (BSIT) often occurs in the transient process between the conducting-state and the blocking-state, so a profound understanding of the physical mechanism of the switching process is of significance for designing and fabricating perfect devices. The dynamical characteristics of the transient process between conducting-state and blocking-state BSITs are represented in detail in this paper. The influences of material, structural and technological parameters on the dynamical performances of BSITs are discussed. The mechanism underlying the transient conversion process is analyzed in depth. The technological approaches are developed to improve the dynamical characteristics of BSITs.

  • Improvement of the efficiency droop of GaN-LEDs using an AlGaN/GaN superlattice insertion layer

    Ji Panfeng, Liu Naixin, Wei Tongbo, Liu Zhe, Lu Hongxi, Wang Junxi, Li Jinmin

    J. Semicond.  2011, 32(11): 114006

    doi: 10.1088/1674-4926/32/11/114006

    Abstract PDF Get Citation

    With an n-AlGaN (4 nm)/GaN (4 nm) superlattice (SL) inserted between an n-GaN and an InGaN/GaN multiquantum well active layer, the efficiency droop of GaN-based LEDs has been improved. When the injection current is lower than 100 mA, the lumen efficiency of the LED with an n-AlGaN/GaN SL is relatively small compared to that without an n-AlGaN/GaN SL. However, as the injection current increases more than 100 mA, the lumen efficiency of the LED with an n-AlGaN/GaN SL surpasses that of an LED without an n-AlGaN/GaN SL. The wall plug efficiency of an LED has the same trend as lumen efficiency. The improvement of the efficiency droop of LEDs with n-AlGaN/GaN SLs can be attributed to a decrease in electron leakage due to the enhanced current spreading ability and electron blocking effect at high current densities. The reverse current of LEDs at -5 V reverse voltage decreases from 0.2568029 to 0.0070543 μA, and the electro-static discharge (ESD) pass yield of an LED at human body mode (HBM)-ESD impulses of 2000 V increases from 60% to 90%.

  • Improved III-nitrides based light-emitting diodes anti-electrostatic discharge capacity with an AlGaN/GaN stack insert layer

    Li Zhicong, Li Panpan, Wang Bing, Li Hongjian, Liang Meng, Yao Ran, Li Jing, Deng Yuanming, Yi Xiaoyan, Wang Guohong, Li Jinmin

    J. Semicond.  2011, 32(11): 114007

    doi: 10.1088/1674-4926/32/11/114007

    Abstract PDF Get Citation

    Through insertion of an AlGaN/GaN stack between the u-GaN and n-GaN of GaN-based light-emitting diodes (LEDs), the strain in the epilayer was increased, the dislocation density was reduced. GaN-based LEDs with different Al compositions were compared. 6.8% Al composition in the stacks showed the highest electrostatic discharge (ESD) endurance ability at the human body mode up to 6000 V and the pass yield exceeded 95%.


  • SOI-based radial-contour-mode micromechanical disk resonator

    Jia Yingqian, Zhao Zhengping, Yang Yongjun, Hu Xiaodong, Li Qian

    J. Semicond.  2011, 32(11): 115001

    doi: 10.1088/1674-4926/32/11/115001

    Abstract PDF Get Citation

    This paper reports a radial-contour-mode micromechanical disk resonator for radio frequency applications. This disk resonator with a gold plated layer as the electrodes, was prepared on a silicon-on-insulator wafer, which is supported by an anchor on another silicon wafer through Au-Au thermo-compression bonding. The gap between the disk and the surrounding gold electrodes is 100 nm. The radius of the disk is 20 μm and the thickness is 4.5 μm. In results, the resonator shows a resonant frequency of 143 MHz and a quality factor of 5600 in vacuum.

  • A wideband RF amplifier for satellite tuners

    Hu Xueqing, Gong Zheng, Shi Yin, Dai Fa Foster

    J. Semicond.  2011, 32(11): 115002

    doi: 10.1088/1674-4926/32/11/115002

    Abstract PDF Get Citation

    This paper presents the design and measured performance of a wideband amplifier for a direct conversion satellite tuner. It is composed of a wideband low noise amplifier (LNA) and a two-stage RF variable gain amplifier (VGA) with linear gain in dB and temperature compensation schemes. To meet the system linearity requirement, an improved distortion compensation technique and a bypass mode are applied on the LNA to deal with the large input signal. Wideband matching is achieved by resistive feedback and an off-chip LC-ladder matching network. A large gain control range (over 80 dB) is achieved by the VGA with process voltage and temperature compensation and dB linearization. In total, the amplifier consumes up to 26 mA current from a 3.3 V power supply. It is fabricated in a 0.35-μ m SiGe BiCMOS technology and occupies a silicon area of 0.25 mm2.

  • LC voltage controlled oscillator in 0.18-μm RF CMOS

    Li Wenyuan, Li Xian, Wang Zhigong

    J. Semicond.  2011, 32(11): 115003

    doi: 10.1088/1674-4926/32/11/115003

    Abstract PDF Get Citation

    An integrated low-phase-noise voltage-controlled oscillator (VCO) has been designed and fabricated in SMIC 0.18 μm RF CMOS technology. The circuit employs an optimally designed LC resonator and a differential cross-coupling amplifier acts as a negative resistor to compensate the energy loss of the resonator. To extend the frequency tuning range, a three-bit binary-weighted switched capacitor array is used in the circuit. The testing result indicates that the VCO achieves a tuning range of 60% from 1.92 to 3.35 GHz. The phase noise of the VCO is -117.8 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz. It draws 5.6 mA current from a 1.8 V supply. The VCO integrated circuit occupies a die area of 600 × 900 μm2. It can be used in the IEEE802.11b based wireless local network receiver.

  • High performance QVCO design with series coupling in CMOS technology

    Cai Li, Huang Lu, Ying Yutong, Fu Zhongqian, Wang Weidong

    J. Semicond.  2011, 32(11): 115004

    doi: 10.1088/1674-4926/32/11/115004

    Abstract PDF Get Citation

    A high performance quadrature voltage-controlled oscillator (QVCO) is presented. It has been fabricated in SMIC 0.18 μ m CMOS technology with top thick metal. The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation. Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise. A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO. The measured phase noise of the proposed QVCO achieves phase noise of -123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz, while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply. The QVCO can operate from 4.09 to 4.87 GHz (17.5%). Measured tuning gain of the QVCO (Kvco) spans from 44.5 to 66.7 MHz/V. The chip area excluding the pads and ESD protection circuit is 0.41 mm2.

  • Noise in a CMOS digital pixel sensor

    Zhang Chi, Yao Suying, Xu Jiangtao

    J. Semicond.  2011, 32(11): 115005

    doi: 10.1088/1674-4926/32/11/115005

    Abstract PDF Get Citation

    Based on the study of noise performance in CMOS digital pixel sensor (DPS), a mathematical model of noise is established with the pulse-width-modulation (PWM) principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS.

  • An 8-18 GHz broadband high power amplifier

    Wang Lifa, Yang Ruixia, Wu Jingfeng, Li Yanlei

    J. Semicond.  2011, 32(11): 115006

    doi: 10.1088/1674-4926/32/11/115006

    Abstract PDF Get Citation

    An 8-18 GHz broadband high power amplifier (HPA) with a hybrid integrated circuit (HIC) is designed and fabricated. This HPA is achieved with the use of a 4-fingered micro-strip Lange coupler in a GaAs MMIC process. In order to decrease electromagnetic interference, a multilayer AlN material with good heat dissipation is adopted as the carrier of the power amplifier. When the input power is 25 dBm, the saturated power of the continuous wave (CW) outputted by the power amplifier is more than 39 dBm within the frequency range of 8-13 GHz, while it is more than 38.6 dBm within other frequency ranges. We obtain the peak power output, 39.4 dBm, at the frequency of 11.9 GHz. In the whole frequency band, the power-added efficiency is more than 18%. When the input power is 18 dBm, the small signal gain is 15.7 ± 0.7 dB. The dimensions of the HPA are 25 × 15 × 1.5 mm3.

  • A digitally controlled PWM/PSM dual-mode DC/DC converter

    Zhen Shaowei, Zhang Bo, Luo Ping, Hou Sijian, Ye Jingxin, Ma Xiao

    J. Semicond.  2011, 32(11): 115007

    doi: 10.1088/1674-4926/32/11/115007

    Abstract PDF Get Citation

    A digitally controlled pulse width modulation/pulse skip modulation (PWM/PSM) dual-mode buck DC/DC converter is proposed. Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode (DCM). The converter works in PSM at DCM and in 2 MHz PWM at CCM. Switching loss is reduced at a light load by skipping cycles. Thus high conversion efficiency is realized in a wide load current. The implementations of PWM control blocks, such as the ADC, the digital pulse width modulator (DPWM) and the loop compensator, and PSM control blocks are described in detail. The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals. The chip is manufactured in 0.13 μm CMOS technology and the chip area is 1.21 mm2. Experimental results show that the conversion efficiency is high, being 90% at 200 mA and 67% at 20 mA. Meanwhile, the measured load step response shows that the proposed dual-mode converter has good stability.

  • A 10-bit 100-MS/s CMOS pipelined folding A/D converter

    Li Xiaojuan, Yang Yintang, Zhu Zhangming

    J. Semicond.  2011, 32(11): 115008

    doi: 10.1088/1674-4926/32/11/115008

    Abstract PDF Get Citation

    This paper presents a 10-bit 100-MSample/s analog-to-digital (A/D) converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network. Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution. In SMIC 0.18 μm CMOS, the A/D converter is measured as follows: the peak integral nonlinearity and differential nonlinearity are ±0.48 LSB and ±0.33 LSB, respectively. Input range is 1.0 VP-P with a 2.29 mm2 active area. At 20 MHz input @ 100 MHz sample clock, 9.59 effective number of bits, 59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved. The dissipation power is only 95 mW with a 1.8 V power supply.

  • A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

    Lei Qianqian, Chen Zhiming, Gong Zheng, Shi Yin

    J. Semicond.  2011, 32(11): 115009

    doi: 10.1088/1674-4926/32/11/115009

    Abstract PDF Get Citation

    This paper presents a 200 mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current, is served as the second stage for a stable frequency response. The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18 μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630 × 550 μm2 and the quiescent current is 130 μA.

  • A novel model for a planar wideband Marchand balun

    Xu Leijun, Wang Zhigong, Li Qin

    J. Semicond.  2011, 32(11): 115010

    doi: 10.1088/1674-4926/32/11/115010

    Abstract PDF Get Citation

    A new lumped element model for conventional Marchand baluns is presented. Analyzed by the even- and odd-mode method, the equivalent equations are derived for λ/4 coupled lines. Based on the proposed 5th-order lumped equivalent circuit for λ/4 coupled lines, the self-inductance, mutual inductive coupling and the capacitance can be calculated according to the even- and odd-mode characteristic impedance, therefore, the model parameters of the balun can be easily gained from the derived equations. To verify the model, a GaAs monolithic wideband Marchand balun was implemented and tested. The EM simulation and experimental results show a good agreement with the model simulation. This model is available in a wide frequency range and makes the design procedure of the Marchand balun faster and easier.

  • A 140 mV 0.8 μA CMOS voltage reference based on sub-threshold MOSFETs

    Yang Miao, Sun Weifeng, Xu Shen, Wang Yifeng, Lu Shengli

    J. Semicond.  2011, 32(11): 115011

    doi: 10.1088/1674-4926/32/11/115011

    Abstract PDF Get Citation

    A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabricated in an SMIC 0.13 μm CMOS process with only MOS transistors and resistors. The experimental results show a reference voltage variation of 2 mV for a supply voltage ranging from 0.5 to 1.2 V and 0.8 mV for temperatures from -20 to 120 ℃. The proposed circuit generates a reference voltage of 140 mV and consumes a supply current of 0.8 μA at room temperature. The occupied area is only 0.019 mm2.

  • A low reference spur quadrature phase-locked loop for UWB systems

    Fu Haipeng, Cai Deyun, Ren Junyan, Li Wei, Li Ning

    J. Semicond.  2011, 32(11): 115012

    doi: 10.1088/1674-4926/32/11/115012

    Abstract PDF Get Citation

    This paper presents a low phase noise and low reference spur quadrature phase-locked loop (QPLL) circuit that is implemented as a part of a frequency synthesizer for China UWB standard systems. A glitch-suppressed charge pump (CP) is employed for reference spur reduction. By forcing the phase frequency detector and CP to operate in a linear region of its transfer function, the linearity of the QPLL is further improved. With the proposed series-quadrature voltage-controlled oscillator, the phase accuracy of the QPLL is guaranteed. The circuit is fabricated in the TSMC 0.13 μm CMOS process and operated at 1.2-V supply voltage. The QPLL measures a phase noise of -95 dBc/Hz at 100-kHz offset and a reference spur of -71 dBc. The fully-integrated QPLL dissipates a current of 13 mA.

  • A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18 μm standard CMOS process

    Feng Peng, Zhang Qi, Wu Nanjian

    J. Semicond.  2011, 32(11): 115013

    doi: 10.1088/1674-4926/32/11/115013

    Abstract PDF Get Citation

    This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor, an RF/analog front-end circuit, an NVM memory and a digital baseband in a standard CMOS process. The sensor with a low power sigma-delta (ΣΔ) ADC is designed to operate in low and high resolution modes. It can not only achieve the target accuracy but also reduce the power consumption and the sensing time. A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip. The 192-bit-NVM tag chip with an area of 1 mm2 is implemented in a 0.18-μm standard CMOS process. The sensitivity of the tag is -10.7 dBm/-8.4 dBm when the sensor is disabled/enabled. It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP. The inaccuracy of the sensor is -0.6 ℃/0.5 ℃ (-1.0 ℃/1.2 ℃) in the operating range from 5 to 15 ℃ in high resolution mode (-30 to 50 ℃ in low resolution mode). The resolution of the sensor achieves 0.02 ℃ (0.18 ℃) in high (low) resolution mode.

  • Indium bump array fabrication on small CMOS circuit for flip-chip bonding

    Huang Yuyang, Zhang Yuxiang, Yin Zhizhen, Cui Guoxin, Liu H C, Bian Lifeng, Yang Hui, Zhang Yaohui

    J. Semicond.  2011, 32(11): 115014

    doi: 10.1088/1674-4926/32/11/115014

    Abstract PDF Get Citation

    We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator. A chip holder with a via hole is used to coat the photoresist for indium bump lift-off. The 1000 μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500 μm, which ensures the integrity of the indium bump array. 64 × 64 indium arrays with 20 μm-high, 30 μm-diameter bumps are successfully formed on a 5 × 6.5 mm2 CMOS chip.

  • A cryogenic SAR ADC for infrared readout circuits

    Zhao Hongliang, Zhao Yiqiang, Zhang Zhisheng

    J. Semicond.  2011, 32(11): 115015

    doi: 10.1088/1674-4926/32/11/115015

    Abstract PDF Get Citation

    A cryogenic successive approximation register (SAR) analog to digital converter (ADC) is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit's performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature (from room temperature down to 77 K) operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity (DNL) and 0.59 LSB maximum integral nonlinearity (INL). It achieves 9.3 bit effective number of bits (ENOB) with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm2.

  • Analysis and optimization of current sensing circuit for deep sub-micron SRAM

    Wang Yiqi, Zhao Fazhan, Liu Mengxin, Lü Yinxue, Zhao Bohua, Han Zhensheng

    J. Semicond.  2011, 32(11): 115016

    doi: 10.1088/1674-4926/32/11/115016

    Abstract PDF Get Citation

    A quantitative yield analysis of a traditional current sensing circuit considering the random dopant fluctuation effect is presented. It investigates the impact of transistor size, falling time of control signal CS and threshold voltage of critical transistors on failure probability of current sensing circuit. On this basis, we present a final optimization to improve the reliability of current sense amplifier. Under 90 nm process, simulation shows that failure probability of current sensing circuit can be reduced by 80% after optimization compared with the normal situation and the delay time only increases marginally.

  • Novel SEU hardened PD SOI SRAM cell

    Xie Chengmin, Wang Zhongfang, Wang Xihu, Wu Longsheng, Liu Youbao

    J. Semicond.  2011, 32(11): 115017

    doi: 10.1088/1674-4926/32/11/115017

    Abstract PDF Get Citation

    A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.

  • Graph theory for FPGA minimum configurations

    Ruan Aiwu, Li Wenchang, Xiang Chuanyin, Song Jiangmin, Kang Shi, Liao Yongbo

    J. Semicond.  2011, 32(11): 115018

    doi: 10.1088/1674-4926/32/11/115018

    Abstract PDF Get Citation

    A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations. This method is limited if a large number of LUTs and multiplexers are presented. Since graph theory has been extensively applied to circuit analysis and test, this paper focuses on the modeling FPGA configurations. In our study, an internal logic block and interconnections of an FPGA are considered as a vertex and an edge connecting two vertices in the graph, respectively. A top-down modeling method is proposed in the paper to achieve minimum configuration numbers for CLB and IOB. Based on the proposed modeling approach and exhaustive analysis, the minimum configuration numbers for CLB and IOB are five and three, respectively.


  • Effect of copper slurry on polishing characteristics

    Hu Yi, Liu Yuling, Liu Xiaoyan, Wang Liran, He Yangang

    J. Semicond.  2011, 32(11): 116001

    doi: 10.1088/1674-4926/32/11/116001

    Abstract PDF Get Citation

    The composition of the polishing solution is optimized by investigating the impact of the WIWNU (the so-called within-wafer-non-uniformity WIWNU) and the removal rate (RR) on the polishing characteristics of copper. The oxidizer concentration is 1 Vol%; the abrasive concentration is 0.8 Vol%; the chelating agent of the solution is 2 Vol%. The working pressure is 1 kPa. The defect on the surface is degraded and the surface is clean after polishing. The removal rate is 289 nm/min and the WIWNU is 0.065. The surface roughness measured by AFM after CMP (chemical mechanical planarization) is 0.22 nm.


Advanced Search >>


XML 地图 | Sitemap 地图