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Volume 31, Issue 9, Sep 2010

    SEMICONDUCTOR PHYSICS

  • Phonon-induced magnetoresistance oscillations in a high-mobility quantum well

    Zhou Qisheng, Cao Juncheng, Qi Ming, Lei Xiaolin

    J. Semicond.  2010, 31(9): 092001

    doi: 10.1088/1674-4926/31/9/092001

    Abstract PDF Get Citation

    We examine the temperature dependence of acoustic-phonon-induced magnetoresistance oscillations in a high-mobility GaAs-based quantum well with conventional transverse and longitudinal phonon modes, using a model in which the temperature increase of the Landau level broadening or the single-particle scattering rate 1/τs is attributed to the enhancement of electron-phonon scattering with rising temperature. The non-monotonic temperature behavior, showing an optimal temperature at which a given order of oscillation amplitude exhibits a maximum and the shift of the main resistance peak to higher magnetic field with rising temperature, is produced, in agreement with recent experimental findings.

  • Frequency of the transition spectral line of an electron in quantum rods

    Wang Guiwen, Xiao Jinglin

    J. Semicond.  2010, 31(9): 092002

    doi: 10.1088/1674-4926/31/9/092002

    Abstract PDF Get Citation

    The Hamiltonian of a quantum rod with an ellipsoidal boundary is given after a coordinate transformation which changes the ellipsoidal boundary into a spherical one. We then study the first internal excited state energy, the excitation energy and the frequency of the transition spectral line between the first internal excited state and the ground state of the strong-coupling polaron in a quantum rod. The effects of the electron–phonon coupling strength, the aspect ratio of the ellipsoid, the transverse radius of quantum rods and the transverse and longitudinal effective confinement length are taken into consideration by using a linear combination operator and the unitary transformation methods. It is found that the first internal excited state energy, the excitation energy and the frequency of the transition spectral line are increasing functions of the electron–phonon coupling strength, whereas they are decreasing ones of the transverse radius of quantum rods and the aspect ratio. The first internal excited state energy, the excitation energy and the frequency of the transition spectral line increase with decreasing transverse and longitudinal effective confinement length. oindent

  • SEMICONDUCTOR MATERIALS

  • Epitaxial growth of ZnO on GaN/sapphire substrate by radio-frequency magnetron sputtering

    Yang Xiaoli, Chen Nuofu, Yin Zhigang, Zhang Xingwang, Li Yang, You Jingbi, Wang Yu, Dong Jingjing, Cui Min, Gao Yun, Huang Tianmao, Chen Xiaofeng, Wang Yanshuo

    J. Semicond.  2010, 31(9): 093001

    doi: 10.1088/1674-4926/31/9/093001

    Abstract PDF Get Citation

    Zinc oxide (ZnO) thin films were grown on n-GaN/sapphire substrates by radio-frequency (RF) magnetron sputtering. The films were grown at substrate temperatures ranging from 400 to 700 ℃ for 1 h at a RF power of 80 W in pure Ar gas ambient. The effect of the substrate temperature on the structural and optical properties of these films was investigated by X-ray diffraction (XRD), atomic force microscopy (AFM) and photoluminescence (PL) spectra. XRD results indicated that ZnO films exhibited wurtzite symmetry and c-axis orientation when grown epitaxially on n-GaN/sapphire. The best crystalline quality of the ZnO film is obtained at a growth temperature of 600 ℃. AFM results indicate that the growth mode and degree of epitaxy strongly depend on the substrate temperature. In PL measurement, the intensity of ultraviolet emission increased initially with the rise of the substrate temperature, and then decreased with the temperature. The highest UV intensity is obtained for the film grown at 600 ℃ with best crystallization. oindent

  • SEMICONDUCTOR DEVICES

  • Deep submicron PDSOI thermal resistance extraction

    Bu Jianhui, Bi Jinshun, Xi Linmao, Han Zhengsheng

    J. Semicond.  2010, 31(9): 094001

    doi: 10.1088/1674-4926/31/9/094001

    Abstract PDF Get Citation

    Deep submicron partially depleted silicon on insulator (PDSOI) MOSFETs with H-gate were fabricated based on the 0.35 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences. Because the self-heating effect (SHE) has a great influence on SOI, extractions of thermal resistance were done for accurate circuit simulation by using the body-source diode as a thermometer. The results show that the thermal resistance in an SOI NMOSFET is lower than that in an SOI PMOSFET; and the thermal resistance in an SOI NMOSFET with a long channel is lower than that with a short channel. This offers a great help to SHE modeling and parameter extraction.

  • A Ga-doped ZnO transparent conduct layer for GaN-based LEDs

    Liu Zhen, Wang Xiaofeng, Yang Hua, Duan Yao, Zeng Yiping

    J. Semicond.  2010, 31(9): 094002

    doi: 10.1088/1674-4926/31/9/094002

    Abstract PDF Get Citation

    An 8 μm thick Ga-doped ZnO (GZO) film grown by metal-source vapor phase epitaxy was deposited on a GaN-based light-emitting diode (LED) to substitute for the conventional ITO as a transparent conduct layer (TCL). Electroluminescence spectra exhibited that the intensity value of LED emission with a GZO TCL is markedly improved by 23.6% as compared to an LED with an ITO TCL at 20 mA. In addition, the forward voltage of the LED with a GZO TCL at 20 mA is higher than that of the conventional LED. To investigate the reason for the increase of the forward voltage, X-ray photoelectron spectroscopy was performed to analyze the interface properties of the GZO/p-GaN heterojunction. The large valence band offset (2.24 ± 0.21 eV) resulting from the formation of Ga2O3 in the GZO/p-GaN interface was attributed to the increase of the forward voltage.

  • Reducing the influence of STI on SONOS memory through optimizing added boron implantation technology

    Xu Yue, Yan Feng, Li Zhiguo, Yang Fan, Wang Yonggang, Chang Jianguang

    J. Semicond.  2010, 31(9): 094003

    doi: 10.1088/1674-4926/31/9/094003

    Abstract PDF Get Citation

    The influence of shallow trench isolation (STI) on a 90 nm polysilicon–oxide–nitride–oxide–silicon structure non-volatile memory has been studied based on experiments. It has been found that the performance of edge memory cells adjacent to STI deteriorates remarkably. The compressive stress and boron segregation induced by STI are thought to be the main causes of this problem. In order to mitigate the STI impact, an added boron implantation in the STI region is developed as a new solution. Four kinds of boron implantation experiments have been implemented to evaluate the impact of STI on edge cells, respectively. The experimental results show that the performance of edge cells can be greatly improved through optimizing added boron implantation technology.

  • Analytical charge control model for AlGaN/GaN MIS-HFETs includingan undepleted barrier layer

    Lu Shenghui, Du Jiangfeng, Luo Qian, Yu Qi, Zhou Wei, Xia Jianxin, Yang Mohua

    J. Semicond.  2010, 31(9): 094004

    doi: 10.1088/1674-4926/31/9/094004

    Abstract PDF Get Citation

    An analytical charge control model considering the insulator/AlGaN interface charge and undepleted AlGaN barrier layer is presented for AlGaN/GaN metal–insulator–semiconductor heterostructure field effect transistors (MIS-HFETs) over the entire operation range of gate voltage. The whole process of charge control is analyzed in detail and partitioned into four regions: I—full depletion, II—partial depletion, III—neutral region and IV—electron accumulation at the insulator/AlGaN interface. The results show that two-dimensional electron gas (2DEG) saturates at the boundary of region II/III and the gate voltage should not exceed the 2DEG saturation voltage in order to keep the channel in control. In addition, the span of region II accounts for about 50% of the range of gate voltage before 2DEG saturates. The good agreement of the calculated transfer characteristic with the measured data confirms the validity of the proposed model.

  • Numerical study of the sub-threshold slope in T-CNFETs

    Zhou Hailiang, Hao Yue, Zhang Minxuan

    J. Semicond.  2010, 31(9): 094005

    doi: 10.1088/1674-4926/31/9/094005

    Abstract PDF Get Citation

    The most attractive merit of tunneling carbon nanotube field effect transistors (T-CNFETs) is the ultra-small inverse sub-threshold slope. In order to obtain as small an average sub-threshold slope as possible, several effective approaches have been proposed based on a numerical insight into the working mechanism of T-CNFETs: tuning the doping level of source/drain leads, minimizing the quantum capacitance value via tuning the bias condition or increasing the insulator capacitance, and adopting a staircase doping strategy in the drain lead. Non-equilibrium Green's function based simulation results show that all these approaches can contribute to a smaller average inverse sub-threshold slope, which is quite desirable in high-frequency or low-power applications.

  • Off-state avalanche breakdown induced degradation in 20 V NLDMOS devices

    Zhang Shifeng, Ding Koubao, Han Yan, Han Chenggong, Hu Jiaxian, Zhang Bin

    J. Semicond.  2010, 31(9): 094006

    doi: 10.1088/1674-4926/31/9/094006

    Abstract PDF Get Citation

    Degradation behaviors of 20 V NLDMOS operated under off-state avalanche breakdown conditions are presented. A constant current pulse stressing test is applied to the device. Two different degradation mechanisms are identified by analysis of electrical data, technology computer-aided design (TCAD) simulations and charge pumping measurements. The first mechanism is attributed to positive oxide-trapped charges in the N-type drift region, and the second one is due to decreased electron mobility upon interface state formation in the drift region. Both of the mechanisms are enhanced with increasing avalanche breakdown current.

  • Ultra high-speed InP/InGaAs SHBTs with ft and fmax of 185 GHz

    Zhou Lei, Jin Zhi, Su Yongbo, Wang Xiantai, Chang Hudong, Xu Anhuai, Qi Ming

    J. Semicond.  2010, 31(9): 094007

    doi: 10.1088/1674-4926/31/9/094007

    Abstract PDF Get Citation

    An InP/InGaAs single heterojunction bipolar transistor (SHBT) with high maximum oscillation frequency (fmax) and high cutoff frequency (ft) is reported. Efforts have been made to maximize fmax and ft simultaneously including optimizing the epitaxial structure, base–collector mesa over-etching and base surface preparation. The measured ft and fmax both reached 185 GHz with an emitter size of 1 × 20 μm2, which is the highest fmax for SHBTs in mainland China. The device is suitable for ultra-high speed digital circuits and low power analog applications.

  • Fabrication of a 120 nm gate-length lattice-matched InGaAs/InAlAsInP-based HEMT

    Huang Jie, Guo Tianyi, Zhang Haiying, Xu Jingbo, Fu Xiaojun, Yang Hao, Niu Jiebin

    J. Semicond.  2010, 31(9): 094008

    doi: 10.1088/1674-4926/31/9/094008

    Abstract PDF Get Citation

    A new PMMA/PMGI/ZEP520/PMGI four-layer resistor electron beam lithography technology is successfully developed and used to fabricate a 120 nm gate-length lattice-matched In0.53Ga0.47As/In0.52Al0.48As InP-based HEMT, of which the material structure is successfully designed and optimized by our group. A 980 nm ultra-wide T-gate head, which is nearly as wide as 8 times the gatefoot (120 nm), is successfully obtained, and the excellent T-gate profile greatly reduces the parasitic resistance and capacitance effect and effectively enhances the RF performances. These fabricated devices demonstrate excellent DC and RF performances such as a maximum current gain frequency of 190 GHz and a unilateral power-gain gain frequency of 146 GHz.

  • Luminescence distribution and hole transport in asymmetric InGaN multiple-quantum well light-emitting diodes

    Ji Xiaoli, Yang Fuhua, Wang Junxi, Duan Ruifei, Ding Kai, Zeng Yiping, Wang Guohong, Li Jinmin

    J. Semicond.  2010, 31(9): 094009

    doi: 10.1088/1674-4926/31/9/094009

    Abstract PDF Get Citation

    Asymmetric InGaN/GaN multiple-quantum well (MQW) light-emitting diodes were fabricated to expose the luminescence distribution and explore the hole transport. Under electrical injection, the sample with a wNQW active region in which the first QW nearest the p-side (QW1) is wider than the subsequent QWs shows a single long-wavelength light-emission peak arising from QW1. The inverse nWQW sample with a narrow QW1 shows one short-wavelength peak and one long-wavelength peak emitted separately from QW1 and the subsequent QWs. Increasing the barrier thickness between QW1 and the second QW (QWB1) in the nWQW structure, the long-wavelength peak is suppressed and the total light-emission intensity decreases. It was concluded that the nWQW and thin-QWB1 structure can improve the hole transport, and hence enhance the light-emission from the subsequent QWs and increase the internal quantum efficiency.

  • In situ growth monitoring of AlGaN/GaN distributed Bragg reflectors at 530 nm using a 633 nm laser

    Wen Feng, Huang Lirong, Jiang Bo, Tong Liangzhu, Xu Wei, Liu Deming

    J. Semicond.  2010, 31(9): 094010

    doi: 10.1088/1674-4926/31/9/094010

    Abstract PDF Get Citation

    The metal-organic chemical vapor deposition (MOCVD) growth of AlGaN/GaN distributed Bragg reflectors (DBR) with a reflection peak at 530 nm was in situ monitored using 633 nm laser reflectometry. Evolutions of in situ reflected reflectivity for different kinds of AlGaN/GaN DBR were simulated by the classical transfer matrix method. Two DBR samples, which have the same parameters as the simulated structures, were grown by MOCVD. The simulated and experimental results show that it is possible to evaluate the DBR parameters from the envelope shape of the in situ reflectivity spectrum. With the help of the 633 nm laser reflectometry, a DBR light emitting diode (LED) was grown. The room temperature photoluminescence spectra show that the reflection peak of the DBR in the LED is within the design region.

  • Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

    Yu Junting, Li Binqiao, Yu Pingping, Xu Jiangtao, Mou Cun

    J. Semicond.  2010, 31(9): 094011

    doi: 10.1088/1674-4926/31/9/094011

    Abstract PDF Get Citation

    Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model. Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment, PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer. With the computer analysis tool ISE-TCAD, simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0 × 1012 cm–2, an implant tilt of –2o, a transfer gate channel doping dose of 3.0 × 1012 cm-2 and an operation voltage of 3.4 V. The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.

  • A novel high voltage start up circuit for an integrated switched mode power supply

    Hu Hao, Chen Xingbi

    J. Semicond.  2010, 31(9): 094012

    doi: 10.1088/1674-4926/31/9/094012

    Abstract PDF Get Citation

    A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • A dual-band frequency synthesizer for CMMB application with low phase noise

    Yu Peng, Yan Jun, Shi Yin, Dai Fa Foster

    J. Semicond.  2010, 31(9): 095001

    doi: 10.1088/1674-4926/31/9/095001

    Abstract PDF Get Citation

    A wide-band frequency synthesizer with low phase noise is presented. The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range. This PLL is fabricated with 0.35 μ m SiGe BiCMOS technology. The measured result shows that the RMS phase error is less than 1o and the reference spur is less than –60 dBc. The proposed PLL consumes 20 mA current from a 2.8 V supply. The silicon area occupied without PADs is 1.17 mm2.

  • A 0.5–1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

    Jiao Yishu, Zhou Yumei, Jiang Jianhua, Wu Bin

    J. Semicond.  2010, 31(9): 095002

    doi: 10.1088/1674-4926/31/9/095002

    Abstract PDF Get Citation

    This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixed-signal SoCs with a wide range of operating frequencies. The design proposes a multi-regulator PLL architecture, in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator, reducing the parasitic noise and spur coupling between different PLL building blocks. Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-fvco/1%-VDD. The design is fabricated in 0.13 μm 1.5/3.3 V CMOS technology. The in-band phase noise of –102
     dBc/Hz at 1 MHz offset with a spur of less than –45 dBc is measured from 1.25 GHz carrier. The measured RMS jitter of the proposed PLL is 1.72 ps at a 1.25 GHz operating frequency. The total power consumption is 19 mW, and its active area is 0.19 mm2.

  • Sigma–delta modulator modeling analysis and design

    Ge Binjie, Wang Xin'an, Zhang Xing, Feng Xiaoxing, Wang Qingqin

    J. Semicond.  2010, 31(9): 095003

    doi: 10.1088/1674-4926/31/9/095003

    Abstract PDF Get Citation

    This paper introduces a new method for SC sigma–delta modulator modeling. It studies the integrator's different equivalent circuits in the integrating and sampling phases. This model uses the OP-AMP input pair's tail current (I0) and overdrive voltage (von) as variables. The modulator's static and dynamic errors are analyzed. A group of optimized I0 and von for maximum SNR and power × area ratio can be obtained through this model. As examples, a MASH21 modulator for digital audio and a second order modulator for RFID baseband are implemented and tested, and they can achieve 91 dB and 72 dB respectively, which verifies the modeling and design criteria.

  • A 1.25 Gb/s laser diode driver with pulse width optimization

    Wang Huan, Wang Zhigong, Xu Jian, Wang Rong, Miao Peng, Luo Yin

    J. Semicond.  2010, 31(9): 095004

    doi: 10.1088/1674-4926/31/9/095004

    Abstract PDF Get Citation

    A 1.25 Gb/s laser diode driver (LDD) with pulse width optimization has been implemented in a 0.6-μm BiCMOS process. This paper illustrates the relation between the pulse width distortion (PWD) of the output eye diagram and the driving amplitude from the second pre-amplifier. Also, a specific current setting circuit working together with an LDD is proposed to generate the optimum driving amplitude and to avoid device nonlinearity, temperature variation and process deviation. The measured results show a maximum crossing deviation of –3% and indicate the desired independence and stability.

  • A 3–5 GHz BPSK transmitter for IR-UWB in 0.18 μm CMOS

    Fu Delong, Huang Lu, Cai Li, Lin Fujiang

    J. Semicond.  2010, 31(9): 095005

    doi: 10.1088/1674-4926/31/9/095005

    Abstract PDF Get Citation

    This paper presents a transmitter IC with BPSK modulation for an ultra-wide band system. It is based on up-conversion with a high linearity passive mixer. Unlike the traditional BPSK modulation scheme, the local oscillator (LO) is modulated by the baseband data instead of the pulse. The chip is designed and fabricated by standard 0.18 μ m CMOS technology. The transmitter achieves a high data rate up to 400 Mbps. The amplitude of the pulse can be adjusted by the amplitude of the LO and the bias current of the driver amplifier. The maximum peak-to-peak amplitude of the pulse is 600 mV. It consumes only 20.3 mA current with a supply voltage of 1.8 V when transmitting a pulse at the maximum data rate. The energy efficiency is 91.4 pJ/pulse. The die area is 1.4 × 1.4 mm2.

  • A reconfigurable OTA-C baseband filter with wide digital tuning for GNSS receivers

    Pan Wenguang, Ma Chengyan, Gan Yebing, Ye Tianchun

    J. Semicond.  2010, 31(9): 095006

    doi: 10.1088/1674-4926/31/9/095006

    Abstract PDF Get Citation

    The design of a digitally-tunable sixth-order reconfigurable OTA-C filter in a 0.18-μm RFCMOS process is proposed. The filter can be configured as a complex band pass filter or two real low pass filters. An improved digital automatic frequency tuning scheme based on the voltage controlled oscillator technique is adopted to compensate for process variations. An extended tuning range (above 8 : 1) is obtained by using widely continuously tunable transconductors based on digital techniques. In the complex band pass mode, the bandwidth can be tuned from 3 to 24 MHz and the center frequency from 3 to 16 MHz.

  • Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process

    Xu Bulu, Shao Bowen, Lin Xia, Yi Wei, Liu Yun

    J. Semicond.  2010, 31(9): 095007

    doi: 10.1088/1674-4926/31/9/095007

    Abstract PDF Get Citation

    Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q2 random walk NMOS current source layout routing method, a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process. The total consumption is only 10 mW from a single 1.2-V power supply, and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively. When the output signal frequency is 1–5 MHz at 100-MSPS sampling rate, the SFDR is measured to be 70 dB. The die area is about 0.2 mm2.

  • A 6–9 GHz ultra-wideband CMOS PA for China's ultra-wideband standard

    Gao Zhendong, Li Zhiqiang, Zhang Haiying

    J. Semicond.  2010, 31(9): 095008

    doi: 10.1088/1674-4926/31/9/095008

    Abstract PDF Get Citation

    A 6–9 GHz ultra-wideband CMOS power amplifier (PA) for the high frequency band of China's UWB standard is proposed. Compared with the conventional band-pass filter wideband input matching methodology, the number of inductors is saved by the resistive feedback complementary amplifying topology presented. The output impendence matching network utilized is very simple but efficient at the cost of only one inductor. The measured S22 far exceeds that of similar work. The PA is designed and fabricated with TSMC 0.18 μm 1P6M RF CMOS technology. The implemented PA achieves a power gain of 10 dB with a ripple of 0.6 dB, and S11 < –10 dB over 6–9 GHz, S22 < –35 dB over 4–10 GHz. The measured output power at the 1 dB compression point is over 3.5 dBm from 6 to 9 GHz. The PA dissipates a total power of 21 mW from a 1.8 V power supply. The chip size is 1.1 × 0.8 mm2.

  • A low power automatic gain control loop for a receiver

    Li Guofeng, Geng Zhiqing, Wu Nanjian

    J. Semicond.  2010, 31(9): 095009

    doi: 10.1088/1674-4926/31/9/095009

    Abstract PDF Get Citation

    This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μm CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μA while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).

  • A high precision high PSRR bandgap reference with thermal hysteresis protection

    Yang Yintang, Li Yani, Zhu Zhangming

    J. Semicond.  2010, 31(9): 095010

    doi: 10.1088/1674-4926/31/9/095010

    Abstract PDF Get Citation

    To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits, a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations. In addition, an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed. Based on the CSMC 0.5 μm 20 V BCD process, the designed circuit is implemented; the active die area is 0.17 × 0.20 mm2. Simulation and testing results show that the temperature coefficient is 13.7 ppm/K with temperature ranging from –40 to 150 ℃, the power supply rejection ratio is –98.2 dB, the line regulation is 0.3 mV/V, and the power consumption is only 0.38 mW. The proposed bandgap voltage reference has good characteristics such as small area, low power consumption, good temperature stability, high power supply rejection ratio, as well as low line regulation. This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog, digital and mixed systems.

  • An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB

    Fan Hua, Wei Qi, Kobenge Sekedi Bomeh, Yin Xiumei, Yang Huazhong

    J. Semicond.  2010, 31(9): 095011

    doi: 10.1088/1674-4926/31/9/095011

    Abstract PDF Get Citation

    This paper presents a differential successive approximation register analog-to-digital converter (SAR ADC) with a novel time-domain comparator design for wireless sensor networks. The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process. The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz. With the Nyquist input frequency, 68.49-dB SFDR, 7.97-ENOB is achieved. A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout. The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.

  • A 10-bit 100-Msps low power time-interleaved ADC using OTA sharing

    Xu Lai, Yin Xiumei, Yang Huazhong

    J. Semicond.  2010, 31(9): 095012

    doi: 10.1088/1674-4926/31/9/095012

    Abstract PDF Get Citation

    A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers, and OTA is shared among the channels for low power dissipation. Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing, increasing the accuracy of each channel and global passive sampling respectively. The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement. The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply. Fabricated in a 180-nm CMOS process, the core of the prototype occupies an area of 2.5 × 1.5 mm2, achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.

  • A 2-GS/s 6-bit self-calibrated flash ADC

    Zhang Youtao, Li Xiaopeng, Zhang Min, Liu Ao, Chen Chen

    J. Semicond.  2010, 31(9): 095013

    doi: 10.1088/1674-4926/31/9/095013

    Abstract PDF Get Citation

    A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μm CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.

  • A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-μm CMOS

    Zhang Zhang, Yuan Yudan, Guo Yawei, Cheng Xu, Zeng Xiaoyang

    J. Semicond.  2010, 31(9): 095014

    doi: 10.1088/1674-4926/31/9/095014

    Abstract PDF Get Citation

    A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented. For the sake of lower power and area, the pipelined stages are scaled in current and area, and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range, poor analog characteristic devices, the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference. Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio, 67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal. The FoM is 0.33 pJ/step. The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB, respectively. The ADC core area is 0.94 mm2.

  • Soft error generation analysis in combinational logic circuits

    Ding Qian, Wang Yu, Luo Rong, Wang Hui, Yang Huazhong

    J. Semicond.  2010, 31(9): 095015

    doi: 10.1088/1674-4926/31/9/095015

    Abstract PDF Get Citation

    Reliability is expected to become a big concern in future deep sub-micron integrated circuits design. Soft error rate (SER) of combinational logic is considered to be a great reliability problem. Previous SER analysis and models indicated that glitch width has a great impact on electrical masking and latch window masking effects, but they failed to achieve enough insights. In this paper, an analytical glitch generation model is proposed. This model shows that after an inflexion point the collected charge has an exponential relationship with glitch duration and the model only introduces an estimation error of on average 2.5%.

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