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Volume 31, Issue 7, Jul 2010


  • The Bipolar Field-Effect Transistor: VIII. Longitudinal Gradient of Longitudinal Electric Field (Two-MOS-Gates on Pure-Base)

    Jie Binbin, Sah Chihtang

    J. Semicond.  2010, 31(7): 071001

    doi: 10.1088/1674-4926/31/7/071001

    Abstract PDF Get Citation

    This paper evaluates the electric current terms from the longitudinal gradient of the longitudinal electric field in Bipolar Field-Effect-Transistors (BiFETs) with a pure base and two MOS gates operating in the unipolar (electron) current mode. These nMOS-BiFETs, known as nMOS-FinFETs, usually have electrically short channels compared with their intrinsic Debye length of about 25 μm at room temperatures. These longitudinal electric current terms are important short-channel current components, which have been neglected in the computation of the long-channel electrical characteristics. This paper shows that the long-channel electrical characteristics are substantially modified by the longitudinal electrical current terms when the physical channel length is less than 100 nm.


  • Electronic and optical properties of the doped TiO2 system

    Zhao Wei, Wang Mei, Su Xiyu, Wang Yachao, Li Zhenyong

    J. Semicond.  2010, 31(7): 072001

    doi: 10.1088/1674-4926/31/7/072001

    Abstract PDF Get Citation

    By the total energy pseudo-potential approach of plane wave, we study the electronic and optical properties of the anatase TiO2 systems with Sc-doped, oxygen vacancies included, and Sc and oxygen vacancies co-existing, respectively. The obtained results show that the contribution by the doped Sc lies mainly in the valence band, and the light absorption in the visible region is obvious. A Mott phase transformation takes place in the presence of oxygen vacancies, and the light absorption in the visible region is also obvious. In particular, the absorption in the visible region of the co-doped system is enhanced coherently due to the influences both from doped Sc and oxygen vacancies.


  • Size-independent growth of pure zinc blende GaAs nanowires

    Ye Xian, Huang Hui, Guo Jingwei, Ren Xiaomin, Huang Yongqing, Wang Qi

    J. Semicond.  2010, 31(7): 073001

    doi: 10.1088/1674-4926/31/7/073001

    Abstract PDF Get Citation

    Pure zinc blende GaAs nanowires were grown by metal organic chemical vapor deposition on GaAs (111) B substrates via Au catalyzed vapor-liquid-solid mechanism. We found that the grown nanowires are rod-like in shape and have a pure zinc blende structure; moreover, the growth rate is independent on its diameters. It can be concluded that, direct impingement of vapor species onto the Au--Ga droplets contributes to the growth of the nanowire; in contrast, the adatom diffusion makes little contribution. The results indicate that the droplet acts as a catalyst rather than an adatom collector, larger diameter and high supersatuation in the droplet leads to the pure zinc blende structure of the nanowire.


  • Barrier height and ideality factor dependency on identically produced small Au/p-Si Schottky barrier diodes

    M. A. Yeganeh, S. H. Rahmatollahpur

    J. Semicond.  2010, 31(7): 074001

    doi: 10.1088/1674-4926/31/7/074001

    Abstract PDF Get Citation

    Small high-quality Au/P-Si Schottky barrier diodes (SBDs) with an extremely low reverse leakage current using wet lithography were produced. Their effective barrier heights (BHs) and ideality factors from current--voltage (I--V) characteristics were measured by a conducting probe atomic force microscope (C-AFM). In spite of the identical preparation of the diodes there was a diode-to-diode variation in ideality factor and barrier height parameters. By extrapolating the plots the built in potential of the Au /p-Si contact was obtained as Vbi = 0.5425 V and the barrier height value Φ B(C - V) was calculated to be ΦB(C - V) = 0.7145 V for Au/p-Si. It is found that for the diodes with diameters smaller than 100 μ m, the diode barrier height and ideality factor dependency to their diameters and correlation between the diode barrier height and its ideality factor are nonlinear, where similar to the earlier reported different metal semiconductor diodes in the literature, these parameters for the here manufactured diodes with diameters more than 100 μ m are also linear. Based on the very obvious sub-nanometer C-AFM produced pictures the scientific evidence behind this controversy is also explained.

  • CuPc based organic-inorganic hetero-junction with Au electrodes

    Zubair Ahmad, Muhammad H. Sayyad, Kh. S. Karimov

    J. Semicond.  2010, 31(7): 074002

    doi: 10.1088/1674-4926/31/7/074002

    Abstract PDF Get Citation

    A hetero-junction of n-silicon (n-Si) and copper phthalocyanine (CuPc) has been fabricated. The current-voltage characteristics were investigated to explain the rectification and conduction mechanism. The effect of temperature and humidity on the electrical properties of n-Si/CuPc hetero-junction has also been investigated. The characteristics of the junction have been observed to be temperature and humidity dependent, so it is suggested that this junction can be used as a temperature and humidity sensor.

  • Monolithic integration of widely tunable sampled grating DBR laser with tilted semiconductor optical amplifier

    Liu Yang, Ye Nan, Wang Baojun, Zhou Daibing, An Xin, Bian Jing, Pan Jiaoqing, Zhao Lingjuan, Wang Wei

    J. Semicond.  2010, 31(7): 074003

    doi: 10.1088/1674-4926/31/7/074003

    Abstract PDF Get Citation

    High output powers and wide range tuning have been achieved in a sampled grating distributed Bragg reflector laser with an integrated semiconductor optical amplifier. Tilted amplifier and anti-reflection facet coating are used to suppress reflection. We have demonstrated sampled grating DBR laser with a tuning range over 38 nm, good wavelength coverage and peak output powers of more than 9 mW for all wavelengths.

  • Fabrication of 17 × 17 polymer/Si arrayed waveguide grating with flat spectral response using steam-redissolution technique

    Qin Zhengkun, He Fei, Liu Chunling, Wang Lizhong, Ma Chunsheng

    J. Semicond.  2010, 31(7): 074004

    doi: 10.1088/1674-4926/31/7/074004

    Abstract PDF Get Citation

    Arrayed waveguide grating (AWG) is a key device in the wavelength-division multiplexing (WDM) system, and the flat spectral response of the AWG device is required. In this paper, the RIE process has been improved. By using the steam-redissolution technique, the insertion loss and the crosstalk have been reduced. Experimental results show that the central wavelength is 1550.86 nm, the channel spectral response flatness is about 1.5 dB, 3-dB bandwidth is about 0.478 nm, insertion loss is 10.5 dB, and crosstalk is about -22 dB. The insertion loss of an AWG device is reduced by about 3 dB for the central channel and 4.5 dB for the edge channels, and the crosstalk is reduced by 2.5 dB after the steam-redissolution.

  • A revised approach to Schottky parameter extraction for GaN HEMT

    Wang Xinhua, Zhao Miao, Liu Xinyu, Zheng Yingkui, Wei Ke

    J. Semicond.  2010, 31(7): 074005

    doi: 10.1088/1674-4926/31/7/074005

    Abstract PDF Get Citation

    We carry out a thermal storage research on GaN HEMT at 350 oC for 48 h, and a recess phenomenon is observed in the low voltage section of Schottky forward characteristics. The decrease of 2DEG density will be responsible for the recess phenomenon. Because the conventional method is not suitable for this kind of curve, a revised approach is presented by analyzing the back-to-back Schottky junction energy band to extract Schottky parameters, which leads to a consistent fit effect.

  • Hot carrier effects of SOI NMOS

    Chen Jianjun, Chen Shuming, Liang Bin, Liu Biwei, Liu Zheng, Teng Zheqian

    J. Semicond.  2010, 31(7): 074006

    doi: 10.1088/1674-4926/31/7/074006

    Abstract PDF Get Citation

    Hot carrier effect (HCE) is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS. Based on the chemical reaction equation of HCE degradation and a geometry dependent reaction diffusion equation, a HCE degradation model for annular NMOS and two-edged NMOS is proposed. According to this model, we conclude that the time exponent of the threshold voltage degradation depends on the configuration of the gate, and annular NMOS has more serious HCE degradation than two-edged NMOS. The design, fabrication and HCE experiments of these NMOS in a 0.5-μm PD SOI process verify the correctness of the conclusion.

  • Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination

    Zhang Qian, Zhang Yuming, Zhang Yimen

    J. Semicond.  2010, 31(7): 074007

    doi: 10.1088/1674-4926/31/7/074007

    Abstract PDF Get Citation

    According to the avalanche ionization theory, a computer-based analysis is performed to analyze the structural parameters of single- and multiple-zone junction termination extension (JTE) structures for 4H-SiC bipolar junction transistors (BJTs) with mesa structure. The calculation results show that a single-zone JTE can yield high breakdown voltages if the activated JTE dose and the implantation width are controlled precisely and a multiple-zone JTE method can decrease the peak surface field while still maintaining a high blocking capability. The influences of the positive and negative surface or interface states on the blocking capability are also shown. These conclusions have a realistic meaning in optimizing the design of a mesa power device.

  • 120-nm gate-length In0.7Ga0.3As/In0.52Al0.48As InP-based HEMT

    Huang Jie, Guo Tianyi, Zhang Haiying, Xu Jingbo, Fu Xiaojun, Yang Hao, Niu Jiebin

    J. Semicond.  2010, 31(7): 074008

    doi: 10.1088/1674-4926/31/7/074008

    Abstract PDF Get Citation

    120 nm gate-length In0.7Ga0.3As/In0.52Al0.48As InP-based high electron mobility transitions (HEMTs) are fabricated by a new T-shaped gate electron beam lithograph (EBL) technology, which is achieved by the use of a PMMA/PMGI/ZEP520/PMGI four-layer photoresistor stack. These devices also demonstrate excellent DC and RF characteristics: the transconductance, maximum saturation drain-to-source current, threshold voltage, maximum current gain frequency, and maximum power-gain cutoff frequency of InGaAs/InAlAs HEMTs is 520 mS/mm, 446 mA/mm, -1.0 V, 141 GHz and 120 GHz, respectively. The material structure and all the device fabrication technology in this work were developed by our group.

  • Influence of the external component on the damage of the bipolar transistor induced by the electromagnetic pulse

    Xi Xiaowen, Chai Changchun, Ren Xingrong, Yang Yintang, Ma Zhenyang, Wang Jing

    J. Semicond.  2010, 31(7): 074009

    doi: 10.1088/1674-4926/31/7/074009

    Abstract PDF Get Citation

    A study on the influence of the external resistor and the external voltage source during the injection of the electromagnetic pulse (EMP) into the bipolar transistor (BJT) is carried out. Research shows that the increase of the external resistor Rb at base makes the burnout time of the device decrease slightly, the increase of the external voltage source Vbe at base can aid the damage of the device when the magnitude of the injecting voltage is relatively low and has little influence when the magnitude is sufficiently high causing the device appearing the PIN structure damage, and the increase of the external resistor Re can remarkably reduce the voltage drops added to the device and improve the durability of the device. In the final analysis, the effect of the external circuit component on the BJT damage is the influence on the condition which makes the device appear current-mode second breakdown.

  • An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor

    Li Binqiao, Yu Junting, Xu Jiangtao, Yu Pingping

    J. Semicond.  2010, 31(7): 074010

    doi: 10.1088/1674-4926/31/7/074010

    Abstract PDF Get Citation

    An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented. This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel. Experimental results show the measured pinch-off voltage is consistent with theoretical prediction. This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sensor.

  • Influence of etching current density on the morphology of macroporous silicon arrays by photo-electrochemical etching

    Wang Guozheng, Chen Li, Qin Xulei, Wang Ji, Wang Yang, Fu Shencheng, Duanmu Qingduo

    J. Semicond.  2010, 31(7): 074011

    doi: 10.1088/1674-4926/31/7/074011

    Abstract PDF Get Citation

    Macroporous silicon arrays (MSA) have attracted much attention for their potential applications in photonic crystals, silicon microchannel plates, MEMS devices and so on. In order to fabricate perfect MSA structure, photo-electrochemical (PEC) etching of MSA and the influence of etching current on the pore morphology were studied in detail. The current--voltage curve of a polished n-type silicon wafer was presented in aqueous HF using back-side illumination. The critical current density JPS was discussed and the basic condition of etching current density for steady MSA growth was proposed. An indirect method was presented to measure the relation of J_PS at the pore tip and etching time. MSA growth was realized with the pore diameter constant by changing the etching current density according to the measuring result of JPS. MSA with 295 μ m of depth and 98 of aspect ratio was obtained.

  • An 8 GHz high power AlGaN/GaN HEMT VCO

    Chen Huifang, Wang Xiantai, Chen Xiaojuan, Luo Weijun, Liu Xinyu

    J. Semicond.  2010, 31(7): 074012

    doi: 10.1088/1674-4926/31/7/074012

    Abstract PDF Get Citation

    A high power X-band hybrid microwave integrated voltage controlled oscillator (VCO) based on AlGaN/GaN HEMT is presented. The oscillator design utilizes a common-gate negative resistance structure with open and short-circuit stub microstrip lines as the main resonator for a high Q factor. The VCO operating at 20 V drain bias and -1.9 V gate bias exhibits an output power of 28 dBm at the center frequency of 8.15 GHz with an efficiency of 21%. Phase noise is estimated to be -85 dBc/Hz at 100 kHz offset and -128 dBc/Hz at 1 MHz offset. The tuning range is more than 50 MHz. The dominating effect of GaN HEMT's flicker noise on oscillator phase noise performance has also been discussed. The measured results show great promise for AlGaN/GaN HEMT technology to be used in high power and low phase noise microwave source applications.

  • A novel dual-functional MEMS sensor integrating both pressure and temperature units

    Chen Tao, Zhang Zhaohua, Ren Tianling, Miao Gujin, Zhou Changjian, Lin Huiwang, Liu Litian

    J. Semicond.  2010, 31(7): 074013

    doi: 10.1088/1674-4926/31/7/074013

    Abstract PDF Get Citation

    This paper proposes a novel miniature dual-functional sensor integrating both pressure and temperature sensitive units on a single chip. The device wafer of SOI is used as a pizeoresistive diaphragm which features excellent consistency in thickness. The conventional anisotropic wet etching has been abandoned, while ICP etching has been employed to etch out the reference cave to minimize the area of individual device in the way that the 57.4 ℃ slope has been eliminated. As a result, the average cost of the single chip is reduced. Two PN junctions with constant ratio of the areas of depletion regions have also been integrated on the same chip to serve as a temperature sensor, and each PN junction shows high linearity over -40 to 100℃ and low power consumption. The iron implanting process for PN junction is exactly compatible with the piezoresistor, with no additional expenditure. The pressure sensitivity is 86 mV/MPa, while temperature sensitivity is 1.43 mV/℃, both complying with the design objective.


  • A 6-9 GHz 5-band CMOS synthesizer for MB-OFDM UWB

    Chen Pufeng, Li Zhiqiang, Wang Xiaosong, Zhang Haiying, Ye Tianchun

    J. Semicond.  2010, 31(7): 075001

    doi: 10.1088/1674-4926/31/7/075001

    Abstract PDF Get Citation

    An ultra-wideband frequency synthesizer is designed to generate carrier frequencies for 5 bands distributed from 6 to 9 GHz with less than 3 ns switching time. It incorporates two phase-locked loops and one single-sideband (SSB) mixer. A 2-to-1 multiplexer with high linearity is proposed. A modified wideband SSB mixer, quadrature VCO, and layout techniques are also employed. The synthesizer is fabricated in a 0.18 μm CMOS process and operates at 1.5-1.8 V while consuming 40 mA current. The measured phase noise is -128 dBc/Hz at 10 MHz offset, and the sideband rejection is -22 dBc at 7.656 GHz.

  • An 18-bit high performance audio Σ-Δ D/A converter

    Zhang Hao, Huang Xiaowei, Han Yan, Ray C. Cheung, Han Xiaoxia, Wang Hao, Liang Guo

    J. Semicond.  2010, 31(7): 075002

    doi: 10.1088/1674-4926/31/7/075002

    Abstract PDF Get Citation

    A multi-bit quantized high performance sigma-delta (Σ-Δ) audio DAC is presented. Compared to its single-bit counterpart, the multi-bit quantization offers many advantages, such as simpler Σ-Δ modulator circuit, lower clock frequency and smaller spurious tones. With the data weighted average (DWA) mismatch shaping algorithm, element mismatch errors induced by multi-bit quantization can be pushed out of the signal band, hence the noise floor inside the signal band is greatly lowered. To cope with the crosstalk between digital and analog circuits, every analog component is surrounded by a guard ring, which is an innovative attempt. The 18-bit DAC with the above techniques, which is implemented in a 0.18 μm mixed-signal CMOS process, occupies a core area of 1.86 mm2. The measured dynamic range (DR) and peak SNDR are 96 dB and 88 dB, respectively.

  • A low-phase-noise digitally controlled crystal oscillator for DVB TV tuners

    Zhao Wei, Lu Lei, Tang Zhangwen

    J. Semicond.  2010, 31(7): 075003

    doi: 10.1088/1674-4926/31/7/075003

    Abstract PDF Get Citation

    This paper presents a 25-MHz fully-integrated digitally controlled crystal oscillator (DCXO) with automatic amplitude control (AAC). The DCXO is based on Colpitts topology for one-pin solution. The AAC circuit is introduced to optimize the phase noise performance. The automatic frequency control is realized by a 10-bit thermometer-code segmental tapered MOS capacitor array, ensuring a ~35 ppm tuning range and ~0.04 ppm frequency step. The measured phase noise results are -139 dBc/Hz at 1 kHz and -151 dBc/Hz at 10 kHz frequency offset, respectively. The chip consumes 1 mA at 1.8V supply and occupies 0.4 mm2 in a 0.18-μm CMOS process.

  • A 2.2-V 2.9-ppm/℃ BiCMOS bandgap voltage reference with full temperature-range curvature-compensation

    Zhou Zekun, Ma Yingqian, Ming Xin, Zhang Bo, Li Zhaoji

    J. Semicond.  2010, 31(7): 075004

    doi: 10.1088/1674-4926/31/7/075004

    Abstract PDF Get Citation

    A high precision high-order curvature-compensated bandgap reference compatible with the standard BiCMOS process, which uses a simple structure to realize a novel exponential curvature compensation in lower temperature ranges, and a piecewise curvature correction in higher temperature ranges, is presented. Experiment results of the proposed bandgap reference implemented with a 0.6-μm BCD process demonstrate that a temperature coefficient of 2.9 ppm/℃ is realized at a 3.6-V power supply, a power supply rejection ratio of 85 dB is achieved, and the line regulation is better than 0.318 mV/V for 2.2-5 V supply voltage dissipating a maximum supply current of 45 μA. The active area of the presented bandgap reference is 260 × 240 μm2.

  • A 2.4 GHz high-linearity low-phase-noise CMOS LC-VCO based on capacitance compensation

    Li Zhenrong, Zhuang Yiqi, Li Bing, Jin Gang, Jin Zhao

    J. Semicond.  2010, 31(7): 075005

    doi: 10.1088/1674-4926/31/7/075005

    Abstract PDF Get Citation

    A 2.4 GHz high-linearity low-phase-noise cross-coupled CMOS LC voltage-controlled oscillator (VCO) is implemented in standard 0.18-μm CMOS technology. An equalization structure for tuning sensitivity base on the three-stage distributed biased switched-varactor bank and the differential switched-capacitor bank is adopted to reduce the variations of the VCO gain, achieve high linearity, and optimize the phase-noise performance. Compared to the conventional VCO, the proposed VCO has more constant gain over the entire tuning range. The tuning range is about 18.7% from 2.23 to 2.69 GHz, and the phase noise is -95 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 1-MHz offset from the carrier frequency of 2.42 GHz. The power dissipation is 2.1 mW from a 1.8 V power supply. The active area of this VCO is 500 × 810 μm2.

  • An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

    Zhang Zhang, Yuan Yudan, Guo Yawei, Cheng Xu, Zeng Xiaoyang

    J. Semicond.  2010, 31(7): 075006

    doi: 10.1088/1674-4926/31/7/075006

    Abstract PDF Get Citation

    An 8-b 100-MS/s pipelined analog-to-digital converter (ADC) is presented. Without the dedicated sample-and-hold amplifier (SHA), it achieves figure-of-merit and area 21% and 12% less than the conventional ADC with the dedicated SHA, respectively. The closed-loop bandwidth of op amps in multiplying DAC is modeled, providing guidelines for power optimization. The theory is well supported by transistor level simulations. A 0.18-μm 1P6M CMOS process was used to integrate the ADCs, and the measured results show that the effective number of bits is 7.43 bit and 6.94 bit for 1-MHz and 80-MHz input signal, respectively, at 100 MS/s. The power dissipation is 23.4 mW including voltage/current reference at 1.8-V supply, and FoM is 0.85 pJ/step. The ADC core area is 0.53 mm2. INL is -0.99 to 0.76 LSB, and DNL is -0.49 to 0.56 LSB.

  • A 2-to-2.4-GHz differentially-tuned fractional-N frequency synthesizer for DVB tuner applications

    Meng Lingbu, Lu Lei, Zhao Wei, Tang Zhangwen

    J. Semicond.  2010, 31(7): 075007

    doi: 10.1088/1674-4926/31/7/075007

    Abstract PDF Get Citation

    This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting-terrestrial (DVB-T) receivers. Transfer functions in differentially-tuned PLL are derived and loop parameters are designed. In addition, a fully-differential charge pump is presented. An 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also presented. Test results show that the RMS phase error is less than 0.7o in integer-N mode and less than 1o in fractional-N mode. The implemented frequency synthesizer draws 10 mA from a 1.8-V supply while occupying a die area of about 1-mm2 in a 0.18-μm CMOS process.

  • An A/D interface based on Σ Δ modulator for thermal vacuum sensor ASICs

    Li Jinfeng, Tang Zhen'an

    J. Semicond.  2010, 31(7): 075008

    doi: 10.1088/1674-4926/31/7/075008

    Abstract PDF Get Citation

    A new Σ Δ modulator architecture for thermal vacuum sensor ASICs is proposed. The micro-hotplate thermal vacuum sensor fabricated by surface-micromachining technology can detect the gas pressure from 1 to 105 Pa. The amplified differential output voltage signal of the sensor feeds to the Σ Δ modulator to be converted into digital domain. The presented Σ Δ modulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity. Compared with other feed-forward architectures presented before, the circuit complexity, chip area and power dissipation of the proposed architecture are significantly decreased. The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise. The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz. The circuit has been fabricated in a 0.5 μm 2P3M standard CMOS technology. It occupies an area of 5 mm2 and dissipates 9 mW from a single 3 V power supply. The performance of the modulator meets the requirements of the considered application.

  • Low-power switched-capacitor delta-sigma modulator for EEG recording applications

    Chen Jin, Zhang Xu, Chen Hongda

    J. Semicond.  2010, 31(7): 075009

    doi: 10.1088/1674-4926/31/7/075009

    Abstract PDF Get Citation

    This paper presents a third-order single-loop delta-sigma modulator of a biomedical micro-system for portable electroencephalogram (EEG) monitoring applications. To reduce the power consumption, the loop filter of the proposed modulator is implemented by applying a switched-capacitor structure. The modulator is designed in a 0.35-μm 2P4M standard CMOS process, with an active area of 365 × 290 μm2. Experimental results show that this modulator achieves a 68 dB dynamic range with an input sinusoidal signal of 100 Hz signal bandwidth under a 64 over-sampling ratio. The whole circuit consumes 515 μW under a 2.5 V power supply, which is suitable for portable EEG monitoring.

  • Design of an LDO with capacitor multiplier

    Ying Jianhua, Huang Meng, Huang Yang

    J. Semicond.  2010, 31(7): 075010

    doi: 10.1088/1674-4926/31/7/075010

    Abstract PDF Get Citation

    This paper presents a low quiescent current, highly stable low-drop out (LDO) regulator. In order to reduce capacitor value and control frequency response peak, capacitor multipliers are adopted in the compensation circuit with mathematic calculations. The phase margin is adequate when the load current is 0.1 or 150 mA. Fabricated in an XFAB 0.6 μm CMOS process, the LDO produces 12.2 mV (0.7%) overshoot voltage while the current changes at 770 mA/100 μs with a capacitor load of 10 μF.

  • A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

    Zheng Jiajie, Mo Taishan, Ma Chengyan, Yin Ming

    J. Semicond.  2010, 31(7): 075011

    doi: 10.1088/1674-4926/31/7/075011

    Abstract PDF Get Citation

    This paper presents a novel approach for designing a reconfigurable variable gain amplifier (VGA) for the multi-mode multi-band receiver system RF front-end applications. The configuration, which is comprised of gain circuits, control circuit, DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing. The VGA is realized in 0.18 μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V. The 3 dB bandwidth is about 80 MHz for all levels of control voltage (all gains). Also, the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input. The overall power consumption is less than 3 mA, and die area is 705 × 100 μm2.

  • A dual VCDL DLL based gate driver for zero-voltage-switching DC-DC converter

    Tian Xin, Liu Xiangxin, Li Wenhong

    J. Semicond.  2010, 31(7): 075012

    doi: 10.1088/1674-4926/31/7/075012

    Abstract PDF Get Citation

    This paper presents a dual voltage-controlled-delay-line (VCDL) delay-lock-loop (DLL) based gate driver for a zero-voltage-switching (ZVS) DC-DC converter. Using the delay difference of two VCDLs for the dead time control, the dual VCDL DLL is able to implement ZVS control with high accuracy while keeping good linearity performance of the DLL and low power consumption. The design is implemented in the CSM 2P4M 0.35 μm CMOS process. The measurement results indicate that an efficiency improvement of 2%-4% is achieved over the load current range from 100 to 600 mA at 4 MHz switching frequency with 3.3 V input and 1.3 V output voltage.

  • Analysis and design of power efficient semi-passive RFID tag

    Che Wenyi, Guan Shuo, Wang Xiao, Xiong Tingwen, Xi Jingtian, Tan Xi, Yan Na, Min Hao

    J. Semicond.  2010, 31(7): 075013

    doi: 10.1088/1674-4926/31/7/075013

    Abstract PDF Get Citation

    The analysis and design of a semi-passive radio frequency identification (RFID) tag is presented. By studying the power transmission link of the backscatter RFID system and exploiting a power conversion efficiency model for a multi-stage AC-DC charge pump, the calculation method for semi-passive tag's read range is proposed. According to different read range limitation factors, an intuitive way to define the specifications of tag's power budget and backscatter modulation index is given. A test chip is implemented in SMIC 0.18 μm standard CMOS technology under the guidance of theoretical analysis. The main building blocks are the threshold compensated charge pump and low power wake-up circuit using the power triggering wake-up mode. The proposed semi-passive tag is fully compatible to EPC C1G2 standard. It has a compact chip size of 0.54 mm2, and is adaptable to batteries with a 1.2 to 2.4 V output voltage.

  • Design of high speed LVDS transceiver ICs

    Xu Jian, Wang Zhigong, Niu Xiaokang

    J. Semicond.  2010, 31(7): 075014

    doi: 10.1088/1674-4926/31/7/075014

    Abstract PDF Get Citation

    The design of low-power LVDS (low voltage differential signaling) transceiver ICs is presented. The LVDS transmitter integrates a common-mode feedback control on chip, while a specially designed pre-charge circuit is proposed to improve the speed of the circuit, making the highest data rate up to 622 Mb/s. For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers. In addition, the LVDS receiver also supports the failsafe function. The transceiver chips were verified with the CSMC 0.5-μm CMOS process. The measured results showed that, for the LVDS transmitter with the pre-charge technique proposed, the maximum data rate is higher than 622 Mb/s. The power consumption is 6 mA with a 5-V power supply. The LVDS receiver can work properly with a larger input common mode voltage (0.1-2.4 V) but a differential input voltage as low as 100 mV. The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/s. The chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.


  • Photoelectrochemical etching of uniform macropore array on full 5-inch silicon wafers

    Zhao Zhigang, Guo Jinchuan, Lei Yaohu, Niu Hanben

    J. Semicond.  2010, 31(7): 076001

    doi: 10.1088/1674-4926/31/7/076001

    Abstract PDF Get Citation

    We analyze the two main factors causing non-uniformity of the etched macropore array first, and then a novel photoelectrochemical etching setup for large area silicon wafers is described. This etching setup refined typical etching setups by a water cooling system and a shower-head shaped electrolyte circulator. Experimental results showed that the uniform macropore array on full 5-inch n-type silicon wafers could be fabricated by this etching setup. The morphology of the macropore array can be controlled by adjusting the corresponding etching parameters.

  • A new cleaning process combining non-ionic surfactant with diamond film electrochemical oxidation for polished silicon wafers

    Gao Baohong, Zhu Yadong, Liu Yuling, Wang Shengli, Zhou Qiang, Liu Xiaoyan

    J. Semicond.  2010, 31(7): 076002

    doi: 10.1088/1674-4926/31/7/076002

    Abstract PDF Get Citation

    This paper presents a new cleaning process for particle and organic contaminants on polished silicon wafer surfaces. It combines a non-ionic surfactant with boron-doped diamond (BDD) film anode electrochemical oxidation. The non-ionic surfactant is used to remove particles on the polished wafer's surface, because it can form a protective film on the surface, which makes particles easy to remove. The effects of particle removal comparative experiments were observed by metallographic microscopy, which showed that the 1% v/v non-ionic surfactant achieved the best result. However, the surfactant film itself belongs to organic contamination, and it eventually needs to be removed. BDD film anode electrochemical oxidation (BDD-EO) is used to remove organic contaminants, because it can efficiently degrade organic matter. Three organic contaminant removal comparative experiments were carried out: the first one used the non-ionic surfactant in the first step and then used BDD-EO, the second one used BDD-EO only, and the last one used RCA cleaning technique. The XPS measurement result shows that the wafer's surface cleaned by BDD-EO has much less organic residue than that cleaned by RCA cleaning technique, and the non-ionic surfactant can be efficiently removed by BDD-EO. 


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