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Volume 30, Issue 7, Jul 2009

    SEMICONDUCTOR PHYSICS

  • Prediction model for the diffusion length in silicon-based solar cells

    Cheknane A, Benouaz T

    J. Semicond.  2009, 30(7): 072001

    doi: 10.1088/1674-4926/30/7/072001

    Abstract PDF Get Citation

    A novel approach to compute diffusion lengths in solar cells is presented. Thus, a simulation is done; it aims to give computational support to the general development of a neural networks (NNs), which is a very powerful predictive modelling technique used to predict the diffusion length in mono-crystalline silicon solar cells. Furthermore, the computation of the diffusion length and the comparison with measurement data, using the infrared injection method, are presented and discussed.

  • Ground-state energy of weak-coupling polarons in quantum rods

    Wang Cuitao, Xiao Jinglin, Zhao Cuilan

    J. Semicond.  2009, 30(7): 072002

    doi: 10.1088/1674-4926/30/7/072002

    Abstract PDF Get Citation

    The Hamiltonian of the quantum rod (QR) with an ellipsoidal boundary is given after a coordinate trans-formation. Using the linear-combination operator and unitary transformation methods, the vibrational frequency and the ground-state energy of weak-coupling polarons are obtained. Numerical results illustrate that the vibrational frequency increases with the decrease of the effective radius R0 of the ellipsoidal parabolic potential and the aspect ratio e′ of the ellipsoid, and that the ground-state energy increases with the decrease of the effective radius R0 and the electron-LO-phonon coupling strength α. In addition, the ground-state energy decreases with increasing aspect ratio e′within 0 < e′ < 1 and reaches a minimum when e′ = 1, and then increases with increasing e′ for e′> 1.

  • Preparation and characterization of CuO nanowire arrays

    Yu Dongliang, Ge Chuannan, Du Youwei

    J. Semicond.  2009, 30(7): 072003

    doi: 10.1088/1674-4926/30/7/072003

    Abstract PDF Get Citation

    CuO nanowire arrays were prepared by oxidation of copper nanowires embedded in anodic aluminum oxide (AAO) membranes. The AAO was fabricated in an oxalic acid at a constant voltage. Copper nanowires were formed in the nanopores of the AAO membranes in an electrochemical deposition process. The oxidized copper nanowires at different temperatures were studied. X-ray diffraction patterns confirmed the formation of a CuO phase after calcining at 500 ℃ in air for 30 h. A transmission electron microscopy was used to characterize the nanowire morphologies. Raman spectra were performed to study the CuO nanowire arrays. After measuring, we found that the current–voltage curve of the CuO nanowires is nonlinear.

  • Lower reflectivity and higher minority carrier lifetime of hand-tailored porous silicon

    Zhang Nansheng, Ma Zhongquan, Zhou Chengyue, He Bo

    J. Semicond.  2009, 30(7): 072004

    doi: 10.1088/1674-4926/30/7/072004

    Abstract PDF Get Citation

    Solar cell grade crystalline silicon with very low reflectivity has been obtained by electrochemically selective erosion. The porous silicon (PS) structure with a mixture of nano- and micro-crystals shows good an-tireflection properties on the surface layer, which has potential for application in commercial silicon photovoltaic devices after optimization. The morphology and reflectivity of the PS layers are easily modulated by controlling the electrochemical formation conditions (i.e., the current density and the anodization time). It has been shown that much a lower reflectivity of approximately 1.42% in the range 380–1100 nm is realized by using optimized conditions. In addition, the minority carrier lifetime of the PS after removing the phosphorus silicon layer is measured to be ~3.19 μs. These values are very close to the reflectivity and the minority carrier lifetime of Si3N4 as a passivation layer on a bulk silicon-based solar cell (0.33% and 3.03 μs, respectively).

  • Ag surface plasmon enhanced double-layer antireflection coatings for GaAs solar cells

    Wang Yanshuo, Chen Nuofu, Zhang Xingwang, Yang Xiaoli, Bai Yiming, Cui Min, Wang Yu, Chen Xiaofeng, Huang Tianmao

    J. Semicond.  2009, 30(7): 072005

    doi: 10.1088/1674-4926/30/7/072005

    Abstract PDF Get Citation

    Surface plasmon enhanced antireflection coatings for GaAs solar cells have been designed theoretically. The reflectance of double-layer antireflection coatings (ARCs) with different suspensions of Ag particles is calculated as a function of the wavelength according to the optical interference matrix and the Mie theory. The mean dielectric concept was adopted in the simulations. A significant reduction of reflectance in the spectral region from 300 to 400 nm was found to be beneficial for the design of ARCs. A new SiO2/Ag–ZnS double-layer coating with better antireflection ability can be achieved if the particle volume fraction in ZnS is 1%–2%.

  • SEMICONDUCTOR MATERIALS

  • Characterization of GaN grown on 4H-SiC and sapphire by Raman spectroscopy and high resolution XRD

    Duan Huantao, Gu Wenping, Zhang Jincheng, Hao Yue, Chen Chi, Ni Jinyu, Xu Shengrui

    J. Semicond.  2009, 30(7): 073001

    doi: 10.1088/1674-4926/30/7/073001

    Abstract PDF Get Citation

    The crystal quality, stress and strain of GaN grown on 4H-SiC and sapphire are characterized by high resolution X-ray diffraction (HRXRD) and Raman spectroscopy. The large stress in GaN leads to the generation of a large number of dislocations. The Raman stress is determined by the results of HRXRD. The position and line shape of the A1 longitudinal optical (LO) phonon mode is used to determine the free carrier concentration and electron mobility in GaN. The differences between free carrier concentration and electron mobility in GaN grown on sapphire and 4H-SiC are analyzed.

  • Wet etching and infrared absorption of AlN bulk single crystals

    Li Weiwei, Zhao Youwen, Dong Zhiyuan, Yang Jun, Hu Weijie, Ke Jianhong

    J. Semicond.  2009, 30(7): 073002

    doi: 10.1088/1674-4926/30/7/073002

    Abstract PDF Get Citation

    The defects and the lattice perfection of an AlN (0001) single crystal grown by the physical vapor transport (PVT) method were investigated by wet etching, X-ray diffraction (XRD), and infrared absorption, respectively. A regular hexagonal etch pit density (EPD) of about 4000 cm-2 is observed on the (0001) Al surface of an AlN single crystal. The EPD exhibits a line array along the slip direction of the wurtzite structure, indicating a quite large thermal stress born by the crystal in the growth process. The XRD full width at half maximum (FWHM) of the single crystal is 35 arcsec, suggesting a good lattice perfection. Pronounced infrared absorption peaks are observed at wave numbers of 1790, 1850, 2000, and 3000 cm-1, respectively. These absorptions might relate to impurities O, C, Si and their complexes in AlN single crystals.

  • A novel method for generating a rectangular convex corner compensation structure in an anisotropic etching process

    Zhang Han, Li Weihua

    J. Semicond.  2009, 30(7): 073003

    doi: 10.1088/1674-4926/30/7/073003

    Abstract PDF Get Citation

    Detailed characteristics of three classical rectangular convex corner compensation structures on (100) silicon substrates have been investigated, and their common design steps are summarized. By combining the basic method of a silicon wet anisotropic etching process, a general method of generating compensation structures for a rectangular convex corner is put forward. This calls for the following two steps: define the topological field and fit some borderlines together into practical compensation patterns. The rules, which must be obeyed during this process, are summarized. By introducing this method, some novel compensation patterns for rectangular convex corner structures are created on both (100) and (110) substrates, and finally simulation results are given to prove this new method's validity and applicability.

  • SEMICONDUCTOR DEVICES

  • Improved dual-channel 4H-SiC MESFETs with high doped n-type surface layers and step-gate structure

    Deng Xiaochuan, Zhang Bo, Li Zhaoji, Zhang Yourun

    J. Semicond.  2009, 30(7): 074001

    doi: 10.1088/1674-4926/30/7/074001

    Abstract PDF Get Citation

    An improved dual-channel 4H-SiC MESFET with high doped n-type surface layer and step-gate structure is proposed, and the static and dynamic electrical performances are analyzed. A high doped n-type surface layer is applied to obtain a low source parasitic series resistance, while the step-gate structure is utilized to reduce the gate capacitance by the elimination of the depletion layer extension near the gate edge, thereby improving the RF characteristics and still maintaining a high breakdown voltage and a large drain current in comparison with the published SiC MESFETs with a dual-channel layer. Detailed numerical simulations demonstrate that the gate-to-drain capacitance, the gate-to-source capacitance, and the source parasitic series resistance of the proposed structure are about 4%, 7%, and 18% smaller than those of the dual-channel structure, which is responsible for 1.4 and 6 GHz improvements in the cut-off frequency and the maximum oscillation frequency.

  • Modeling of self-heating effects in polycrystalline silicon thin film transistors

    Deng Wanling, Zheng Xueren

    J. Semicond.  2009, 30(7): 074002

    doi: 10.1088/1674-4926/30/7/074002

    Abstract PDF Get Citation

    An analytical DC model accounting for the self-heating effect of polycrystalline silicon thin-film transistors (poly-Si TFTs) is presented. In deriving the model for the self-heating effect, the temperature dependence of the effective mobility is studied in detail. Based on the mobility model and a first order approximation, a closed-form analytical drain current model considering the self-heating effect is derived. Compared with the available experimental data, the proposed model, which includes the self-heating and kink effects, provides an accurate description of the output characteristics over the linear, the saturation, and the kink regimes.

  • Effect of the back surface topography on the efficiency in silicon solar cells

    Guo Aijuan, Ye Famin, Guo Lihui, Ji Dong, Feng Shimeng

    J. Semicond.  2009, 30(7): 074003

    doi: 10.1088/1674-4926/30/7/074003

    Abstract PDF Get Citation

    Different processes are used on the back surface of silicon wafers to form cells falling into three groups: textured, planar, and sawed-off pyramid back surface. The characteristic parameters of the cells, ISC, VOC, FF, Pm, and Eff, are measured. All these parameters of the planar back surface cells are the best. The FF, Pm, and Eff of sawed-off pyramid back surface cells are superior to textured back surface cells, although ISC and VOC are lower. The parasitic resistance is analyzed to explain the higher FF of the sawed-off pyramid back surface cells. The cross-section scanning electron microscopy (SEM) pictures show the uniformity of the aluminum–silicon alloy, which has an important effect on the back surface recombination velocity and the ohmic contact. The measured value of the aluminum back surface field thickness in the SEM picture is in good agreement with the theoretical value deduced from the Al–Si phase diagram. It is shown in an external quantum efficiency (EQE) diagram that the planar back surface has the best response to a wavelength between 440 and 1000 nm and the sawed-off back surface has a better long wavelength response.

  • A low-loss V-groove coplanar waveguide on an SOI substrate

    Zhao Yuhang, Tong Jiarong, Zeng Xuan, Wang Yong

    J. Semicond.  2009, 30(7): 074004

    doi: 10.1088/1674-4926/30/7/074004

    Abstract PDF Get Citation

    A novel low-loss 50-Ω coplanar waveguide with V-groove on an SOI substrate is proposed. Through a CMOS-compatible process and anisotropic etching of silicon, surface silicon is removed from the SOI. The measured results show that the V-groove coplanar waveguide causes about 50% less loss than the conventional one at a high frequency of up to 40 GHz.

  • Temperature dependence of charge sharing and MBU sensitivity induced by a heavy ion

    Liu Biwei, Chen Shuming, Liang Bin

    J. Semicond.  2009, 30(7): 074005

    doi: 10.1088/1674-4926/30/7/074005

    Abstract PDF Get Citation

    The temperature dependence of charge sharing in a 130 nm CMOS technology has been investigated over a temperature range of 200 to 420 K. Device simulation results show that the charge sharing collection increases by 66%–325% when the temperature rises. The LETth of a MBU in two SRAM cells and one DICE cell is also quantified. Besides charge sharing, the circuit response's temperature dependence also has a significant influence on the LETth.

  • A simple method of measuring differentially-excited on-wafer spiral inductor-like components

    Pan Jie, Yang Haigang, Yang Liwu

    J. Semicond.  2009, 30(7): 074006

    doi: 10.1088/1674-4926/30/7/074006

    Abstract PDF Get Citation

    This paper proposes a simple method of measuring differentially-excited on-wafer RF CMOS spiral inductor-like components. This method requires only two common ‘G-S-G’ probes and an ordinary two-port VNA. Using a network instead of a detailed equivalent circuit, this method completes the de-embedding with only one ‘Through’ dummy, and thus the measurements are greatly simplified. By designing the ports ‘Open’ or ‘Short-circuited’ deliberately, a multi-port transformer can be transformed into three two-port networks with different terminators. Then, couplings between the two coils can be solved, and the differentially-excited scattering parameters (S-parameters) can be constructed. Also, a group of differential inductors and transformers were designed and measured, and then comparisons between simulated and measured electromagnetic results are performed to verify this method.

  • Novel approach for characterizing the specific shunt resistance caused by the penetration of the front contact through the p–n junction in solar cell

    Zhang Lucheng, Shen Hui

    J. Semicond.  2009, 30(7): 074007

    doi: 10.1088/1674-4926/30/7/074007

    Abstract PDF Get Citation

    Shunt can drastically decrease the solar cell conversion efficiency and its current measurement result only reflects the overall shunting effect of all shunts in a whole cell. In order to accurately characterize local shunts caused by the penetration of front contacts through the emitter junction, silicon solar cells with a new structure named beam bridge contact were fabricated. The result showed that the region under the emitter was more badly shunted than the other emitter regions. The sample preparation process was completely compatible with the industrial silicon fabrication sequence, which was of great convenience. The measurement results give informations on the solar cell structure, material ingredients, and process parameters.

  • Boundary condition and initial value effects in the reaction–diffusion model of interface trap generation/recovery

    Luo Yong, Huang Daming, Liu Wenjun, Li Mingfu

    J. Semicond.  2009, 30(7): 074008

    doi: 10.1088/1674-4926/30/7/074008

    Abstract PDF Get Citation

    A simple standard reaction–diffusion (RD) model assumes an infinite oxide thickness and a zero initial interface trap density, which is not the case in real MOS devices. In this paper, we numerically solve the RD model by taking into account the finite oxide thickness and an initial trap density. The results show that trap generation/passivation as a function of stress/recovery time is strongly affected by the condition of the gate-oxide/poly-Si boundary. When an absorbent boundary is considered, the RD model is more consistent with the measured interface-trap data from CMOS devices under bias temperature stress. The results also show that non-negligible initial traps should affect the power index n when a power law of the trap generation with the stress time, tn, is observed in the diffusion limited region of the RD model.

  • Method of simulation of low dose rate for total dose effect in 0.18 μm CMOS technology

    He Baoping, Yao Zhibin, Guo Hongxia, Luo Yinhong, Zhang Fengqi, Wang Yuanming, Zhang Keying

    J. Semicond.  2009, 30(7): 074009

    doi: 10.1088/1674-4926/30/7/074009

    Abstract PDF Get Citation

    Three methods for simulating low dose rate irradiation are presented and experimentally verified by using 0.18 μm CMOS transistors. The results show that it is the best way to use a series of high dose rate irradiations, with 100 ℃ annealing steps in-between irradiation steps, to simulate a continuous low dose rate irradiation. This approach can reduce the low dose rate testing time by as much as a factor of 45 with respect to the actual 0.5 rad (Si)/s dose rate irradiation. The procedure also provides detailed information on the behavior of the test devices in a low dose rate environment.

  • Ultra-low-voltage-trigger thyristor for on-chip ESD protection without extra process cost

    Shan Yi, He Jun, Huang Wenyi

    J. Semicond.  2009, 30(7): 074010

    doi: 10.1088/1674-4926/30/7/074010

    Abstract PDF Get Citation

    A new thyristor is proposed and realized in the foundry's 0.18-μm CMOS process for electrostatic discharge (ESD) protection. Without extra mask layers or process steps, the new ultra-low-voltage-trigger thyristor (ULVT thyristor) has a trigger voltage as low as 6.7 V and an ESD robustness exceeding 50 mA/μm, which enables effective ESD protection. Compared with the traditional medium-voltage-trigger thyristor (MVT thyristor), the new structure not only has a lower trigger voltage, but can also provide better ESD protection under both positive and negative ESD zapping conditions.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • Novel mixed-voltage I/O buffer with thin-oxide CMOS transistors

    Yu Bo, Wang Yuan, Jia Song, Zhang Ganggang

    J. Semicond.  2009, 30(7): 075001

    doi: 10.1088/1674-4926/30/7/075001

    Abstract PDF Get Citation

    This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS process. This mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gate-oxide reliability that the conventional CMOS I/O buffer has. The design is realized in a 0.13-μm CMOS process and the simulation results show a good performance increased by ~34% with respect to the product of power consumption and speed.

  • Effect of a reset-MOSFET in a high-speed comparator

    Liu Haitao, Meng Qiao, Wang Zhigong, Tang Kai

    J. Semicond.  2009, 30(7): 075002

    doi: 10.1088/1674-4926/30/7/075002

    Abstract PDF Get Citation

    A high-speed comparator design based on regeneration architecture, which can be used in a flash ADC, is presented. A threshold-limit-speed effect (TLSE) which limits the speed of the comparator was discovered and studied in detail. The size of the reset-MOSFET was optimized to resolve the TLSE and make the comparator work at the maximal speed. The results were confirmed by simulation and the corresponding circuit was realized in a flash ADC design in SMIC 0.18-μm CMOS technology. The test result shows that the comparator can work well at 2 GHz and can even work up to 2.8 GHz while the power dissipation is 3.2 mW.

  • A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation

    Zheng Yongzheng, Li Weinan, Xia Lingli, Huang Yumei, Hong Zhiliang

    J. Semicond.  2009, 30(7): 075003

    doi: 10.1088/1674-4926/30/7/075003

    Abstract PDF Get Citation

    A fully integrated phase-locked loop (PLL) is presented for a single quadrature output frequency of 3.96 GHz. The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation. An adaptive frequency calibration loop is incorporated into the PLL. The capacitance area in the loop filter is largely reduced through a capacitor multiplier. Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of –70 dBc/Hz at 10 kHz offset and –113 dBc/Hz at 1 MHz offset. The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps. The reference spur level is less than –68 dBc.

  • VLSI architecture of a K-best detector for MIMO–OFDM wireless communication systems

    Jian Haifang, Shi Yin

    J. Semicond.  2009, 30(7): 075004

    doi: 10.1088/1674-4926/30/7/075004

    Abstract PDF Get Citation

    The K-best detector is considered as a promising technique in the MIMO–OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO–OFDM systems.

  • A high precision programmable bandgap voltage reference design for high resolution ADC

    Zhu Tiancheng, Yao Suying, Li Binqiao

    J. Semicond.  2009, 30(7): 075005

    doi: 10.1088/1674-4926/30/7/075005

    Abstract PDF Get Citation

    Bandgap voltage reference is a basic module in a high accuracy analog circuit design. For high resolution ADC, the accuracy of reference voltage is critical for the whole design. A high precision bandgap voltage reference is needed to provide high accuracy reference voltages. A traditional bandgap reference is hard to meet the accuracy requirement for all the technology corners. In this paper, a programmable high precision bandgap reference is presented, which can solve the problem motioned above. This design adopts Smic 0.18 ?m 1P4M CMOS technology. The theoretically achievable temperature coefficient approaches to 0.69 ppm/ °C over the commercial temperature range.

  • A 3–5 GHz TH-UWB transmitter in 0.18-μm RF CMOS technology

    Duan Jihai, Wang Zhigong, Li Zhiqun

    J. Semicond.  2009, 30(7): 075006

    doi: 10.1088/1674-4926/30/7/075006

    Abstract PDF Get Citation

    An RF transmitter is proposed for 35 GHz time-hopping ultra wideband (TH-UWB) wireless applications. The transmitter consists of a 4-GHz oscillator, a switch with a controllable attenuator and an output matching circuit. Through controlling the low frequency signals with time-hopping pulse position modulation (TH-PPM), the circuit supplies TH-UWB signals and can directly drive an antenna by a transmission line. The transmitter was implemented in a 0.18-μm CMOS technology, and the output amplitude is about 65 mV at a 50 ? load from a 1.8-V supply, the return loss (S11) at the output port is less than -10dB, and the chip size is 0.7 × 0.8 mm2, with a power consumption of 12.3 mW.

  • A 2.4-GHz low power dual gain low noise amplifier for ZigBee

    Gao Peijun, Min Hao

    J. Semicond.  2009, 30(7): 075007

    doi: 10.1088/1674-4926/30/7/075007

    Abstract PDF Get Citation

    This paper presents a fully differential dual gain low noise amplifier (DGLNA) for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications. The effect of input parasitics on the inductively degenerated cascode LNA is analyzed. Circuit design details within the guidelines of the analysis are presented. The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process. The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss. In high gain mode, the measured noise figure (NF) is 2.3–3 dB in the whole 2.45-GHz ISM band. The measured 1-dB compression point, IIP3 and IIP2 is –9, 1 and 33 dBm, respectively. The DGLNA consumes 2 mA of current from a 1.8 V power supply.

  • A fractional-N frequency synthesizer forWCDMA/Bluetooth/ZigBee applications

    Zhou Chunyuan, Li Guolin, Zhang Chun, Chi Baoyong, Li Dongmei, Wang Zhihua

    J. Semicond.  2009, 30(7): 075008

    doi: 10.1088/1674-4926/30/7/075008

    Abstract PDF Get Citation

    A triple-mode fractional-N frequency synthesizer with a noise-filter voltage control oscillator (VCO) for WCDMA/Bluetooth/ZigBee applications has been implemented in 0.18 μm RF-CMOS technology. The proposed synthesizer achieves a good phase noise lower than -80 dBc/Hz in band and -115 dBc/Hz @ 1 MHz for the three modes, which only draws 21 mA from 1.8 V supply. It has a high hardware sharing and a small size which is only 1.5 mm × 1.4 mm. The system architecture, circuit design and measured results are presented in this paper.

  • CMOS current controlled fully balanced current conveyor

    Wang Chunhua, Zhang Qiujing, Liu Haiguang

    J. Semicond.  2009, 30(7): 075009

    doi: 10.1088/1674-4926/30/7/075009

    Abstract PDF Get Citation

    This paper presents a current controlled fully balanced second-generation current conveyor circuit (CF-BCCII). The proposed circuit has the traits of fully balanced architecture, and its X–Y terminals are current controllable. Based on the CFBCCII, two biquadratic universal filters are also proposed as its applications. The CFBCCII circuits and the two filters were fabricated with chartered 0.35-μm CMOS technology; with ±1.65 V power supply voltage, the total power consumption of the CFBCCII circuit is 3.6 mW. Comparisons between measured and HSpice simulation results are also given.

  • Optimization design of a full asynchronous pipeline circuit based on null convention logic

    Guan Xuguang, Zhou Duan, Yang Yintang

    J. Semicond.  2009, 30(7): 075010

    doi: 10.1088/1674-4926/30/7/075010

    Abstract PDF Get Citation

    This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline. Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode. The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules. Performance penalty brought by null cycle is reduced while the data processing capacity is increased. The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS technology. Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption. This indicates the new design proposal is preferable for high-speed asynchronous designs due to its high throughput and delay-insensitivity.

  • A high precision CMOS weak current readout circuit

    Wu Qisong, Yang Haigang, Yin Tao, Zhang Chong

    J. Semicond.  2009, 30(7): 075011

    doi: 10.1088/1674-4926/30/7/075011

    Abstract PDF Get Citation

    This paper presents a high precision CMOS weak current readout circuit. This circuit is capable of converting a weak current into a frequency signal for amperometric measurements with high precision and further delivering a 10-bit digital output. A fast stabilization-enhanced potentiostat has been proposed in the design, which is used to maintain a constant bias potential for amperometric biochemical sensors. A technique based on source voltage shifting that reduces the leakage current of the MOS transistor to the reverse diode leakage level at room temperature was employed in the circuit. The chip was fabricated in the 0.35 μm chartered CMOS process, with a single 3.3 V power supply. The interface circuit maintains a dynamic range of more than 100 dB. Currents from 1 pA to 300 nA can be detected with a maximum nonlinearity of 0.3% over the full scale.

  • Low-cost low-power UHF RFID tag with on-chip antenna

    Xi Jingtian, Yan Na, Che Wenyi, Xu Conghui, Wang Xiao, Yang Yuqing, Jian Hongyan, Min Hao

    J. Semicond.  2009, 30(7): 075012

    doi: 10.1088/1674-4926/30/7/075012

    Abstract PDF Get Citation

    This paper presents an EPC Class 1 Generation 2 compatible tag with on-chip antenna implemented in the SMIC 0.18 μm standard CMOS process. The UHF tag chip includes an RF/analog front-end, a digital base-band, and a 640-bit EEPROM memory. The on-chip antenna is optimized based on a novel parasitic-aware model. The rectifier is optimized to achieve a power conversion efficiency up to 40% by applying a self-bias feedback and threshold compensation techniques. A good match between the tag circuits and the on-chip antenna is realized by adjusting the rectifier input impedance. Measurements show that the presented tag can achieve a communication range of 1 cm with 1 W reader output power using a 1 × 1 cm2 single-turn loop reader antenna.

  • A universal programmable driving circuit for spatial light modulators

    Wu Lan, Yu Ningmei, Zhang Yaohui, Ma Wenlong

    J. Semicond.  2009, 30(7): 075013

    doi: 10.1088/1674-4926/30/7/075013

    Abstract PDF Get Citation

    A universal programmable multi-quantum-well (MQW) spatial light modulator (SLM) driving circuit is developed. With a twice scanning, it can generate programmable signals to drive a non-linear MQW SLM by using a software preprocessing unit. By adjusting the switching network of the driving circuit, this circuit can reduce the switching noise and improve the output precision. The chip test results show that the driving voltage can swing from 0 to VDD, and its resolution could be close to 256 with a pixel area of only 65 × 65 μm2.

  • A low power bandgap reference with buffer working in the sub-threshold region for energy harvesting systems

    Jia Chen, Hao Wenhan, Chen Hong, Zhang Chun, Wang Zhihua

    J. Semicond.  2009, 30(7): 075014

    doi: 10.1088/1674-4926/30/7/075014

    Abstract PDF Get Citation

    We propose a bandgap reference, which works in sub-threshold regions to the reduce power consumption in applications such as those in energy harvesting systems that stimulate the development of power management for low power consumption applications.Measurements shows that the supply current of the proposed bandgap reference is only 6.87 μA, including a voltage buffer consuming 3.6 μA of supply current, when the supply voltage is 5 V. The supply voltage can vary from 3 to 11 V and the line regulation of the proposed bandgap reference output voltage is 0.875 mV/V at room temperature. The temperature coefficiency is 88.9 ppm from 10 to 100 ℃ when the supply voltage is 5 V.

  • SEMICONDUCTOR TECHNOLOGY

  • An efficient method for monitoring the shunts in silicon solar cells during fabrication processes with infrared imaging

    Zhang Lucheng, Xu Xinxiang, Yang Zhuojian, Sun Xiaopu, Xu Hongyun, Liu Haobin, Shen Hui

    J. Semicond.  2009, 30(7): 076001

    doi: 10.1088/1674-4926/30/7/076001

    Abstract PDF Get Citation

    In order to monitor the fabrication process, an infrared imaging system was established to detect the shunted regions in crystalline silicon solar cells. The temperature of the shunted region was obviously higher than that of the non-shunted region when the cell was biased under direct voltage due to the Joule heat effect, and the shunted region could be detected by infrared imaging. The shunts caused by seven different reasons can be identified using metallurgical microscopy, scanning electron microscopy, and energy dispersive X-ray spectroscopy. Approaches for diminishing shunts are presented. The methods are beneficial for the optimization of the cell fabrication processes and the improvement of the cell performances.

  • Packaging technology of LEDs for LCD backlights

    Fan Manning, Liang Meng, Wang Guohong

    J. Semicond.  2009, 30(7): 076002

    doi: 10.1088/1674-4926/30/7/076002

    Abstract PDF Get Citation

    We design a package patterned with red and green emitting phosphors excited by a blue LED to emit tri-basic mixing color. For high backlight display quality, we compare several phosphors. According to our measurements, green phosphors 0752G, 0753G and red phosphor 0763R are preferred for producing a good backlight source. Compared to RGB-LED backlight units, this frame typically benefits the lighting uniformity, and can simplify the structures. It also provides higher color render and better CCT than the traditional package method of a yellow phosphor with a blue chip. However, its light efficiency needs to be further improved for the use of backlights for LCDs.

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