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Volume 30, Issue 11, Nov 2009

    SEMICONDUCTOR PHYSICS

  • First principles study of the Be–C co-doped MgB2 system

    Su Xiyu, Zhi Xiaofen, Hou Qinying, Cheng Wei, Liu Jiaxue

    J. Semicond.  2009, 30(11): 112001

    doi: 10.1088/1674-4926/30/11/112001

    Abstract PDF Get Citation

    We study the Be–C doped MgB2 system by the first principles method based on density functional theory. The compensation effect between electron type doping and hole type doping is shown in the total density of states on the Fermi level, the real part of optical conductivity, and the number of effective carriers. The compensation mechanisms are discussed. The critical temperatures for different systems are calculated.

  • Anisotropic polarization due to electron–phonon interactions in graphene

    Li Wuqun, Cao Juncheng

    J. Semicond.  2009, 30(11): 112002

    doi: 10.1088/1674-4926/30/11/112002

    Abstract PDF Get Citation

    Polarization plays an important role in the Raman spectroscopy. We study, in graphene, anisotropic polarization due to electron–phonon coupling (EPC). The numerical results show that the anisotropy is obvious even when the wave vector is in the range of the Raman experiment. The analytical expression is deduced from the structure factor, which indicates the crucial origin of the anisotropy. We also find that, as the phonon energy increases the polarization is clearly weakened due to the screen effect of EPC, but the anisotropy totally remains.

  • Effects of Sn-doping on morphology and optical properties of CdTe polycrystalline films

    Li Jin, Yang Liny, Jian Jikang, Zou Hua, Sun Yanfei

    J. Semicond.  2009, 30(11): 112003

    doi: 10.1088/1674-4926/30/11/112003

    Abstract PDF Get Citation

    Sn-doped CdTe polycrystalline films were successfully deposited on ITO glass substrates by close space sublimation. The effects of Sn-doping on the microstructure, surface morphology, and optical properties of polycrystalline films were studied using X-ray diffraction, scanning electron microscopy, and ultraviolet-visible spectrophotometry, respectively. The results show that the lower molar ratio of Sn and CdTe conduces to a strongly preferential orientation of (111) in films and a larger grain size, which indicates that the crystallinity of films can be improved by appropriate Sn-doping. As the molar ratio of Sn and CdTe increases, the preferential orientation of (111) in films becomes weaker, the grain size becomes smaller, and the crystal boundary becomes indistinct, which indicates that the crystallization growth of films is incomplete. However, as the Sn content increases, optical absorption becomes stronger in the visible region. In summary, a strongly preferential orientation of (111) in films and a larger grain size can be obtained by appropriate Sn-doping (molar ratio of Sn : CdTe = 0.06 : 1), while the film retains a relatively high optical absorption in the visible region. However, Sn-doping has no obvious influence on the energy gap of CdTe films.

  • SEMICONDUCTOR MATERIALS

  • Particular electrical quality of a-plane GaN films grown on r-plane sapphire by metal-organic chemical vapor deposition

    Xu Shengrui, Zhou Xiaowei, Hao Yue, Mao Wei, Zhang Jincheng, Zhang Zhongfen, Bai Lin, Zhang Jinfeng, Li Zhiming

    J. Semicond.  2009, 30(11): 113001

    doi: 10.1088/1674-4926/30/11/113001

    Abstract PDF Get Citation

    Nonpolar (1120) a-plane GaN films have been grown by low-pressure metal-organic vapor deposition on r-plane (1102) sapphire substrate. The structural and electrical properties of the a-plane GaN films are investigated by high-resolution X-ray diffraction (HRXRD), atomic force microscopy (AFM) and van der Pauw Hall measurement. It is found that the Hall voltage shows more anisotropy than that of the c-plane samples; furthermore, the mobility changes with the degree of the van der Pauw square diagonal to the c direction, which shows significant electrical anisotropy. Further research indicates that electron mobility is strongly influenced by edge dislocations.

  • Influence of the distance between target and substrate on the properties of transparent conducting Al–Zr co-doped zinc oxide thin films

    Zhang Huafu, Liu Hanfa, Zhou Aiping, Yuan Changkun

    J. Semicond.  2009, 30(11): 113002

    doi: 10.1088/1674-4926/30/11/113002

    Abstract PDF Get Citation

    Highly transparent and conducting Al–Zr co-doped zinc oxide (ZAZO) thin films were successfully prepared on glass substrate by direct current (DC) magnetron sputtering at room temperature. The distance between target and substrate was varied from 45 to 70 mm. All the deposited films are polycrystalline with a hexagonal structure and have a preferred orientation along the c-axis perpendicular to the substrate. The crystallinity increases obviously and the electrical resistivity decreases when the distance between target and substrate decreases from 70 to 50 mm. However, as the distance decreases further, the crystallinity decreases and the electrical resistivity increases. When the distance between target and substrate is 50 mm, it is found that the lowest resistivity is 6.9E4 Ω·cm. All the deposited films show a high average transmittance of above 92% in the visible range.

  • Characterization of quaternary AlInGaN epilayers and polarization-reduced InGaN/AlInGaN MQWgrown by MOCVD

    Liu Naixin, Wang Junxi, Yan Jianchang, Liu Zhe, Ruan Jun, Li Jinmin

    J. Semicond.  2009, 30(11): 113003

    doi: 10.1088/1674-4926/30/11/113003

    Abstract PDF Get Citation

    We have demonstrated the growth of quaternary AlInGaN compounds at different growth temperatures and pressures with metalorganic chemical vapor deposition (MOCVD). The optical properties of the samples have been investigated by photoluminescence (PL) at different temperatures. The results show that the sample grown at higher temperature (850 ℃) exhibits the best optical quality for its sharp band edge luminescence and weak yellow luminescence. The AlInGaN exhibited three-dimensional (3D) growth mode at higher pressure. The band edge emission almost disappeared. With the optimization of AlInGaN growth parameters, we replaced the traditional barrier in InGaN/GaN multiple quantum wells (MQWs) with AlInGaN barriers. The peak wavelength for the InGaN/AlInGaN-MQW based light emitting diodes (LEDs) was very stable at various injection current levels because of the polarization-matched InGaN/AlInGaN MQWs.

  • Finite element analysis of the temperature field in a vertical MOCVD reactor by induction heating

    Li Zhiming, Xu Shengrui, Zhang Jincheng, Chang Yongming, Ni Jingyu, Zhou Xiaowei, Hao Yue

    J. Semicond.  2009, 30(11): 113004

    doi: 10.1088/1674-4926/30/11/113004

    Abstract PDF Get Citation

    The temperature field in the vertical metalorganic chemical vapor deposition (MOCVD) reactor chamber used for the growth of GaN materials is studied using the finite element analysis method (FEM). The effects of the relative position between the coils and the middle section of the susceptor, the radius of the coil, and the height of the susceptor on heating condition are analyzed. All simulation results indicate that the highest heating efficiency can be obtained under the conditions that the coil distributes symmetrically in the middle section of the susceptor and the ratio of the height of the susceptor to that of the coil is three-quarters. Furthermore, the heating efficiency is inversely proportional to the radius of the coil.

  • SEMICONDUCTOR DEVICES

  • InP/InGaAs heterojunction bipolar transistors with different μ-bridge structures

    Yu Jinyong, Liu Xinyu, Xia Yang

    J. Semicond.  2009, 30(11): 114001

    doi: 10.1088/1674-4926/30/11/114001

    Abstract PDF Get Citation

    Several μ-bridge structures for InP-based heterojunction bipolar transistors (HBTs) are reported. The radio frequency measurement results of these InP HBTs are compared with each other. The comparison shows that μ-bridge structures reduce the parasites and double μ-bridge structures have a better effect. Due to the utilization of the double μ-bridges, both the cutoff frequency fT and also the maximum oscillation frequency fmax of the 2 × 12.5 μm2 InP/InGaAs HBT reach nearly 160 GHz. The results also show that the μ-bridge has a better effect in increasing the high frequency performance of a narrow emitter InP HBT.

  • Fabrication and characteristics of the nc-Si/c-Si heterojunction MAGFET

    Zhao Xiaofeng, Wen Dianzhong

    J. Semicond.  2009, 30(11): 114002

    doi: 10.1088/1674-4926/30/11/114002

    Abstract PDF Get Citation

    AMAGFET using an nc-Si/c-Si heterojunction as source and drain was fabricated by CMOS technology, using two ohm-contact electrodes as Hall outputs on double sides of the channel situated 0.7L from the source. The experimental results show that when VDS = -7.0 V, the magnetic sensitivity of the single nc-Si/c-Si heterojunction magnetic metal oxide semiconductor field effect transistor (MAGFET) with an L : W ratio of 2 : 1 is 21.26 mV/T, and that with an L : W ratio of 4 : 1 is 13.88 mV/T. When the outputs of double nc-Si/c-Si heterojunction MAGFETs with an L : W ratio of 4 : 1 are in series, their magnetic sensitivity is 22.74 mV/T, which is an improvement of about 64% compared with that of a single nc-Si/c-Si heterojunction MAGFET.

  • Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

    Ni Henan, Wu Liangcai, Song Zhitang, Hui Chun

    J. Semicond.  2009, 30(11): 114003

    doi: 10.1088/1674-4926/30/11/114003

    Abstract PDF Get Citation

    An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.

  • Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

    Wu Chia-Song, Liu Hsing-Chung

    J. Semicond.  2009, 30(11): 114004

    doi: 10.1088/1674-4926/30/11/114004

    Abstract PDF Get Citation

    This paper investigates the feasibility of using a lanthanum oxide thin film (La2O3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La2O3 thickness. The thin La2O3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. La2O3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 ℃ because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La2O3 thin film was thermally stable. The DC and RF characteristics of Pt/La2O3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined. The measurements indicated that the transistor with the Pt/La2O3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La2O3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

  • Novel lateral IGBT with n-region controlled anode on SOI substrate

    Chen Wensuo, Xie Gang, Zhang Bo, Li Zehong, Li Zhaoji

    J. Semicond.  2009, 30(11): 114005

    doi: 10.1088/1674-4926/30/11/114005

    Abstract PDF Get Citation

    A new lateral insulated-gate bipolar transistor (LIGBT) structure on SOI substrate, called an n-region controlled anode LIGBT (NCA-LIGBT), is proposed and discussed. The n-region controlled anode concept results in fast switch speeds, efficient area usage and effective suppression NDR in forward I–V characteristics. Simulation results of the key parameters (n-region doping concentration, length, thickness and p-base doping concentration) show that the NCA-LIGBT has a good tradeoff between turn-off time and on-state voltage drop. The proposed LIGBT is a novel device for power ICs such as PDP scan driver ICs.

  • A three-dimensional breakdown model of SOI lateral power transistors with a circular layout

    Guo Yufeng, Wang Zhigong, Sheu Gene

    J. Semicond.  2009, 30(11): 114006

    doi: 10.1088/1674-4926/30/11/114006

    Abstract PDF Get Citation

    This paper presents an analytical three-dimensional breakdown model of SOI lateral power devices with a circular layout. The Poisson equation is solved in cylindrical coordinates to obtain the radial surface potential and electric field distributions for both fully- and partially-depleted drift regions. The breakdown voltages for N+N and P+N junctions are derived and employed to investigate the impact of cathode region curvature. A modified RESURF criterion is proposed to provide a design guideline for optimizing the breakdown voltage and doping concentration in the drift region in three dimensional space. The analytical results agree well with MEDICI simulation results and experimental data from earlier publications.

  • Single-mode GaAs/AlGaAs quantum cascade microlasers

    Gao Yu, Liu Junqi, Liu Fengqi, Zhang Wei, Zhang Quande, Liu Wanfeng, Li Lu, Wang Lijun, Wang Zhanguo

    J. Semicond.  2009, 30(11): 114007

    doi: 10.1088/1674-4926/30/11/114007

    Abstract PDF Get Citation

    Single-mode edge emitting GaAs/AlGaAs quantum cascade microlasers at a wavelength of about 11.4 μm were realized by shortening the Fabry-Perot cavity length. The spacing of the longitudinal resonator modes is inversely proportional to the cavity length. Stable single-mode emission with a side mode suppression ratio of about 19 dB at 85 K for a 150-μm-long device was demonstrated.

  • A linear array of 980 nm VCSEL and its high temperature operation characteristics

    Zhang Yan, Ning Yongqiang, Wang Ye, Liu Guangyu, Wang Zhenfu, Zhang Xing, Shi Jingjing, Zhang Lisen, Wang Wei, Qin Li, Sun Yanfang, Liu Yun, Wang Lijun

    J. Semicond.  2009, 30(11): 114008

    doi: 10.1088/1674-4926/30/11/114008

    Abstract PDF Get Citation

    A 980 nm bottom-emitting vertical-cavity surface-emitting laser linear array with high power density and a good beam property of Gaussian far-field distribution is reported. This array is composed of five linearly arranged elements with a 200 μm diameter one at the center, the other two 150 μm and 100 μm diameter ones at both sides of the center with center to center spacing of 300 μm and 250 μm, respectively. A power of 880 mW at a current of 4 A and a corresponding power density of up to 1 kW/cm2 is obtained. The temperature dependent characteristics of the linear array are investigated. The thermal interaction between the individual elements of the VCSEL linear array is smaller due to its optimized element size and device spacing, which make it more suitable for high power applications. A peak power of over 20 W has been achieved in pulsed operation with a 60 ns pulse length and a repetition frequency of 1 kHz.

  • Estimation of electron mobility of n-doped 4, 7-diphenyl-1, 10-phenanthroline using space-charge-limited currents

    Khizar-ul-Haq, Khan M A, Jiang Xueyin, Zhang Zhilin, Zhang Xiaowen, Zhang Liang, Li Jun

    J. Semicond.  2009, 30(11): 114009

    doi: 10.1088/1674-4926/30/11/114009

    Abstract PDF Get Citation

    The electron mobilities of 4, 7-diphenyl-1, 10-phenanthroline (BPhen) doped 8-hydroxyquinolinato-lithium (Liq) at various thicknesses (50–300 nm) have been estimated by using space-charge-limited current measurements. It is observed that the electron mobility of 33 wt% Liq doped BPhen approaches its true value when the thickness is more than 200 nm. The electron mobility of 33 wt% Liq doped BPhen at 300 nm is found to be ~5.2E-3 cm2/(V·s) (at 0.3 MV/cm) with weak dependence on electric field, which is about one order of magnitude higher than that of pristine BPhen (3.4E-4 cm2/(V·s)) measured by SCLC. For the typical thickness of organic light-emitting devices, the electron mobility of doped BPhen is also investigated.

  • Working mechanism of a SiC nanotube NO2 gas sensor

    Ding Ruixue, Yang Yintang, Liu Lianxi

    J. Semicond.  2009, 30(11): 114010

    doi: 10.1088/1674-4926/30/11/114010

    Abstract PDF Get Citation

    The working mechanism of sensors plays an important role in their simulation and design, which is the foundation of their applications. A model of a nanotube NO2 gas sensor system is established based on an (8, 0) silicon carbide nanotube (SiCNT) with a NO2 molecule adsorbed. The transport properties of the system are studied with a method combining density functional theory (DFT) with the non-equilibrium Green’s function (NEGF). The adsorbed gas molecule plays an important role in the transport properties of the gas sensor, which results in the formation of a transmission peak near the Fermi energy. More importantly, the adsorption leads to different voltage current characteristics of the sensor to that with no adsorption; the difference is large enough to detect the presence of NO2 gas.

  • Modeling and discussion of threshold voltage for a multi-floating gate FET pH sensor

    Shi Zhaoxia, Zhu Dazhong

    J. Semicond.  2009, 30(11): 114011

    doi: 10.1088/1674-4926/30/11/114011

    Abstract PDF Get Citation

    Research into new pH sensors fabricated by the standard CMOS process is currently a hot topic. The new pH sensing multi-floating gate field effect transistor is found to have a very large threshold voltage, which is different from the normal ion-sensitive field effect transistor. After analyzing all the interface layers of the structure, a new sensitive model based on the Gauss theorem and the charge neutrality principle is created in this paper. According to the model, the charge trapped on the multi-floating gate during the process and the thickness of the sensitive layer are the main causes of the large threshold voltage. From this model, it is also found that removing the charge on the multi-floating gate is an effective way to decrease the threshold voltage. The test results for three different standard pH buffer solutions show the correctness of the model and point the way to solve the large threshold problem.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • A 10 GHz high-effciency and low phase-noise negative-resistance oscillator optimized with a virtual loop model

    Wang Xiantai, Jin Zhi, Wu Danyu, Shen Huajun, Liu Xinyu

    J. Semicond.  2009, 30(11): 115001

    doi: 10.1088/1674-4926/30/11/115001

    Abstract PDF Get Citation

    A virtual loop model was built by the transmission analysis with virtual ground method to assist the negative-resistance oscillator design, providing more perspectives on output power and phase-noise optimization. In this work, the virtual loop described the original circuit successfully and the optimizations were effective. A 10 GHz high-efficiency low phase-noise oscillator utilizing an InGaP/GaAs HBT was achieved. The 10.028 GHz oscillator delivered an output power of over 15 dBm with a phase-noise of lower than –107 dBc/Hz at 100 kHz offset. The efficiency of DC to RF transformation was 35%. The results led to a good oscillator figure of merit of –188 dBc/Hz. The measurement results agreed well with those of the simulations.

  • An eighth order channel selection filter for low-IF and zero-IF DVB tuner applications

    Zou Liang, Liao Youchun, Tang Zhangwen

    J. Semicond.  2009, 30(11): 115002

    doi: 10.1088/1674-4926/30/11/115002

    Abstract PDF Get Citation

    An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves –52 dB and the out-band IM3 achieves –55 dB with –11 dBm input power. This proposed filter circuit, fabricated in a SMIC 0.18 μm CMOS process, consumes 4 mA current with 1.8 V power supply.

  • Noise and mismatch optimization for capacitive MEMS readout

    Zhang Chong, Wu Qisong, Yin Tao, Yang Haigang

    J. Semicond.  2009, 30(11): 115003

    doi: 10.1088/1674-4926/30/11/115003

    Abstract PDF Get Citation

    This paper presents a high precision CMOS readout circuit for a capacitive MEMS gyroscope. A continuous time topology is employed as well as the chopper noise cancelling technique. A detailed analysis of the noise and mismatch of the capacitive readout circuit is given. The analysis and measurement results have shown that thermal noise dominates in the proposed circuit, and several approaches should be used for both noise and mismatch optimization. The circuit chip operates under a single 5 V supply, and has a measured capacitance resolution of 0.2 aF/√Hz. With such a readout circuit, the gyroscope can accurately measure the angular rate with a sensitivity of 15.3 mV/?/s.

  • A low power high gain UWB LNA in 0.18-μm CMOS

    Cai Li, Fu Zhongqian, Huang Lu

    J. Semicond.  2009, 30(11): 115004

    doi: 10.1088/1674-4926/30/11/115004

    Abstract PDF Get Citation

    A low power high gain differential UWB low noise amplifier (LNA) operating at 3–5 GHz is presented. A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a –3 dB bandwidth of 2.8–5 GHz, a measured minimum noise figure (NF) of 3.35 dB and –12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm2 including test pads.

  • Realization of an analog predistortion circuit for RF optical fiber links

    Tian Xuenong, Wang Zhigong, Li Wei

    J. Semicond.  2009, 30(11): 115005

    doi: 10.1088/1674-4926/30/11/115005

    Abstract PDF Get Citation

    This paper presents an analog predistortion circuit for RF optical fiber links. The circuit consists of two source-coupled differential transconductance amplifiers which could provide linear and nonlinear transfer characteristics by adjusting the bias voltage and the transistor sizes. The circuit was designed and realized in a standard 0.18-μm CMOS technology of SMIC. The chip occupies 0.48 × 0.24 mm2. The DC supply is 3.3 V. Using this circuit, the third-order intermodulation distortion (IMD) suppression of a directly modulated RF optical fiber link can be improved by 9–16 dBc at relatively low cost.

  • Design of a DTCTGAL circuit and its application

    Wang Pengjun, Li Kunpeng, Mei Fengna

    J. Semicond.  2009, 30(11): 115006

    doi: 10.1088/1674-4926/30/11/115006

    Abstract PDF Get Citation

    By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.

  • A 12-bit 100 MS/s pipelined ADC with digital background calibration

    Zhou Liren, Luo Lei, Ye Fan, Xu Jun, Ren Junyan

    J. Semicond.  2009, 30(11): 115007

    doi: 10.1088/1674-4926/30/11/115007

    Abstract PDF Get Citation

    This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18 μm CMOS process, occupies an active area of 2.3 × 1.6 mm2, and consumes 205 mW at 1.8 V.

  • Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

    Liang Tao, Jia Xinzhang, Chen Junfeng

    J. Semicond.  2009, 30(11): 115008

    doi: 10.1088/1674-4926/30/11/115008

    Abstract PDF Get Citation

    Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven (OPD) metamodels of MOSFETs are introduced to capture the circuit’s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed forMOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.

  • Circuit design of a novel FPGA chip FDP2008

    Wu Fang, Wang Yabin, Chen Liguang, Wang Jian, Lai Jinmei, Wang Yuan, Tong Jiarong

    J. Semicond.  2009, 30(11): 115009

    doi: 10.1088/1674-4926/30/11/115009

    Abstract PDF Get Citation

    A novel FPGA chip FDP2008 (Fudan Programmable Logic) has been designed and implemented with the SMIC 0.18 μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX + Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 × 30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.

  • SEMICONDUCTOR TECHNOLOGY

  • Reduction of proximity effect in fabricating nanometer-spaced nanopillars by two-step exposure

    Zhang Yang, Zhang Renping, Han Weihua, Liu Jian, Yang Xiang, Wang Ying, Li Chian Chiu, Yang Fuhua

    J. Semicond.  2009, 30(11): 116001

    doi: 10.1088/1674-4926/30/11/116001

    Abstract PDF Get Citation

    A two-step exposure method to effectively reduce the proximity effect in fabricating nanometer-spaced nanopillars is presented. In this method, nanopillar patterns on poly-methylmethacrylate (PMMA) were partly cross-linked in the first-step exposure. After development, PMMA between nanopillar patterns was removed, and hence the proximity effect would not take place there in the subsequent exposure. In the second-step exposure, PMMA masks were completely cross-linked to achieve good resistance in inductively coupled plasma etching. Accurate pattern transfer of rows of nanopillars with spacing down to 40 nm was realized on a silicon-on-insulator substrate.

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