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Volume 29, Issue 4, Apr 2008


  • The Bipolar Theory of the Field-Effect Transistor:X.The Fundamental Physics and Theory(All Device Structures)

    Sah Chih-Tang, Jie Binbin

    J. Semicond.  2008, 29(4): 613

    Abstract PDF

    This paper describes the foundation underlying the device physics and theory of the semiconductor field effect transistor which is applicable to any devices with two carrier species in an electric field. The importance of the boundary conditions on the device current-voltage characteristics is discussed. An illustration is given of the transfer DCIV characteristics computed for two boundary conditions,one on electrical potential,giving much higher drift-limited parabolic current through the intrinsic transistor,and the other on the electrochemical potentials,giving much lower injection-over-the-barrier diffusion-limited current with ideal 60mV per decade exponential subthreshold roll-off,simulating electron and hole contacts.The two-MOS-gates on thin pure-body silicon field-effect transistor is used as examples.

  • The Bipolar Field-Effect Transistor:V.Bipolar Electrochemical Current Theory(Two-MOS-Gates on Thin-Base)

    Jie Binbin, Sah Chih-Tang

    J. Semicond.  2008, 29(4): 620

    Abstract PDF

    This paper reports the intrinsic-structure DC characteristics computed from the analytical electrochemical current theory of the bipolar field-effect transistor (BiFET) with two identical MOS gates on nanometer-thick pure-base of silicon with no generation-recombination-trapping.Numerical solutions are rapidly obtained for the three potential variables,electrostatic and electron and hole electrochemical potentials,to give the electron and hole surface and volume channel currents,using our cross-link two-route or zig-zag one-route recursive iteration algorithms. Boundary conditions on the three potentials dominantly affect the intrinsic-structure DC characteristics,illustrated by examples covering 20-decades of current (10E-22 to 10E-2 A/Square at 400cm2/ (V·s) mobility for 1.5nm gate-oxide,and 30nm-thick pure-base). Aside from the domination of carrier space-charge-limited drift current in the strong surface channels,observed in the theory is also the classical drift current saturation due to physical pinch-off of an impure-base volume channel depicted by the 1952 Shockley junction-gate field-effect transistor theory,and its extension to complete cut-off of the pure-base volume channel,due to vanishing carrier screening by the few electron and hole carriers in the pure-base,with Debye length (25mm) much larger than device dimension (25nm).

  • Emerging Challenges in ESD Protection for RF ICs in CMOS

    Wang Albert, Lin Lin, Wang Xin, Liu Hainan, Zhou Yumei

    J. Semicond.  2008, 29(4): 628

    Abstract PDF

    On-chip electrostatic discharge (ESD) protection design has become an emerging challenge for radio-frequency (RF) integrated circuits (IC) design as IC technologies migrate into the very-deep-sub-micron (VDSM) regime and RF ICs move into multi-GHz operations.The key problem originates from the complex interaction between the ESD protection circuitry and the core RF IC circuit under protection.This paper discusses the recent development in RF ESD protection research and design,outlining emerging challenges,new design methods,and novel RF ESD protection solutions.

  • Fabrication of n+ Polysilicon Ohmic Contacts with a Heterojunction Structure to n-Type 4H-Silicon Carbide

    Guo Hui, Feng Qian, Tang Xiaoyan, Zhang Yimen, Zhang Yuming

    J. Semicond.  2008, 29(4): 637

    Abstract PDF

    Polysilicon ohmic contacts to n-type 4H-SiC have been fabricated.TLM (transfer length method) test patterns with polysilicon structure are formed on n-wells created by phosphorus ion (P+) implantation into a Si-faced p-type 4H-SiC epilayer.The polysilicon is deposited using low-pressure chemical vapor deposition (LPCVD) and doped by phosphorous ions implantation followed by diffusion to obtain a sheet resistance of 22Ω/□.The specific contact resistance ρc of n+ polysilicon contact to n-type 4H-SiC as low as 3.82×10-5Ω·cm2 is achieved.The result for sheet resistance Rsh of the phosphorous ion implanted layers in SiC is about 4.9kΩ/□.The mechanisms for n+ polysilicon ohmic contact to n-type SiC are discussed.

  • Smaller Ge Quantum Dots Obtained by ArF Excimer Laser Annealing

    Zeng Yugang, Han Genquan, Yu Jinzhong

    J. Semicond.  2008, 29(4): 641

    Abstract PDF

    Ge self-assembled quantum dots (SAQDs) are grown with a self-assembled UHV/CVD epitaxy system.Then,the as-grown Ge quantum dots are annealed by ArF excimer laser.In the ultra-shot laser pulse duration,~20ns,bulk diffusion is forbidden,and only surface diffusion occurs,resulting in a laser induced quantum dot (LIQD).The diameter of the LIQD is 20~25nm which is much smaller than the as-grown dot and the LIQD has a higher density of about 6E10cm-2.The surface morphology evolution is investigated by AFM.

  • An SIT-BJT Operation Model for SITh in the Blocking State

    Yang Jianhong, Wang Zaixing, Li Siyuan

    J. Semicond.  2008, 29(4): 645

    Abstract PDF

    A SIT-BJT model is proposed for static induction thyristors (SITh) operation in the blocking state.On the basis of the physical mechanism,this model is presented analytically in terms of governing equations that link the electrical parameters to the structural parameters.The model is verified by numerical simulation and theoretical analysis.Based on the model,the variations of the electrical parameters such as the potential barrier,the anode junction voltage drop,and the current amplification factor are studied and discussed.

  • OTFT with Bilayer Gate Insulator and Modificative Electrode

    Bai Yu, Khizar-ul-Haq, M.A.Khan, Jiang Xueyin, Zhang Zhilin

    J. Semicond.  2008, 29(4): 650

    Abstract PDF

    An organic thin-film transistor (OTFT) with an OTS/SiO2 bilayer gate insulator and a MoO3/Al electrode configuration between gate insulator and source/drain electrodes has been investigated.A thermally grown SiO2 layer is used as the OTFT gate dielectric and copper phthalocyanine(CuPc) is used as an active layer.This OTS/SiO2 bilayer gate insulator configuration increases the field-effect mobility,reduces the threshold voltage,and improves the on/off ratio simultaneously.The device with a MoO3/Al electrode has shown similar Ids compared to the device with an Au electrode at the same gate voltage.Our results indicate that using a double-layer of electrodes and a double-layer of insulators is an effective way to improve OTFT performance.

  • A High Purity Integer-N Frequency Synthesizer in 0.35μm SiGe BiCMOS

    Zhang Jian, Li Zhiqiang, Chen Liqiang, Chen Pufeng, Zhang Haiying

    J. Semicond.  2008, 29(4): 655

    Abstract PDF

    An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented.By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized.All the building blocks are implemented with differential topology except for the off-chip loop filter.To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO.The frequency synthesizer operates from 239 to 2.72GHz with output power of about 0dBm.The measured closed-loop phase noise is -95dBc/Hz at 100kHz offset and -116dBc/Hz at 1MHz offset from the carrier.The power level of the reference spur is less than -72dBc.With a 3V power supply,the whole chip including the output buffers consumes 60mA.

  • A Novel All-pMOS AC to DC Charge Pump with High Efficiency

    Jiang Bowei, Wang Xiao, Min Hao

    J. Semicond.  2008, 29(4): 660

    Abstract PDF

    A novel AC to DC charge pump with high performance is presented.Due to the pMOS structure and threshold voltage canceling technology,the efficiency and the output voltage are greatly improved.Test results show that the output voltage and power efficiency are improved by 125% and 104% respectively at 13.56MHz for a 1V sinusoidal input compared to the traditional MOS diodes structure.


  • The Convergence Characteristic of the Forward I-V Characteristic Curves of a Semiconductor Silicon Barrier at Different Temperatures

    Miao Qinghai, Lu Shuojin, Zhang Xinghua, Zong Fujian, Zhu Yangjun

    J. Semicond.  2008, 29(4): 663

    Abstract PDF

    The I-V-(T) characteristic curves of p-n junctions with the forward voltage as the independent variable,the logarithm of forward current as the dependent variable,and the junction temperature as the parameter,almost converge at one point in the first quadrant.The voltage corresponding with the convergence point nearly equals the bandgap of the semiconductor material.This convergence point can be used to obtain the I-V characteristic curve at any temperature.

  • 1.0μm Gate-Length GaAs MHEMT Devices and SPDT Switch MMICs

    Xu Jingbo, Li Ming, Zhang Haiying, Wang Wenxin, Yin Junjian, Liu Liang, Li Xiao, Zhang Jian, Ye Tianchun

    J. Semicond.  2008, 29(4): 668

    Abstract PDF

    1.0μm gate-length GaAs-based MHEMTs have been fabricated by MBE epitaxial material and contact-mode lithography technology.Pt/Ti/Pt/Au and Ti/Pt/Au were evaporated to form gate metals.Excellent DC and RF performances have been obtained,and the transconductance,maximum saturation drain current density,threshold voltage,current cut-off frequency,and maximum oscillation frequency of Pt/Ti/Pt/Au and Ti/Pt/Au MHEMTs were 502(503)mS/mm,382(530)mA/mm,0.1(-0.5)V,13.4(14.8)GHz,and 17.0(17.5)GHz,respectively.DC-10GHz single-pole double-throw (SPDT) switch MMICs have been designed and fabricated by Ti/Pt/Au MHEMTs.Insertion loss,isolation,input,and output return losses of SPDT chips were better than 2.93,23.34,and 20dB.

  • A Novel Equivalent Circuit Model of GaAs PIN Diodes

    Wu Rufei, Zhang Haiying, Yin Junjian, Li Xiao, Liu Huidong, Liu Xunchun

    J. Semicond.  2008, 29(4): 672

    Abstract PDF

    A novel equivalent circuit model for a GaAs PIN diode is presented based on physical analysis.The diode is divided into three parts:the p+n- junction,the i-layer,and the n-n+ junction,which are modeled separately.The entire model is then formed by combining the three sub-models.In this way,the model’s accuracy is greatly enhanced.Furthermore,the corresponding parameter extraction method is easy,requiring no rigorous experiment or measurement.To validate this newly proposed model,fifteen groups of diodes are fabricated.Measurement shows that the model exactly represents behavior of GaAs PIN diodes under both forward and reversely biased conditions.

  • An Ultra-Low Specific On-Resistance VDMOS with a Step Oxide-Bypassed Trench Structure

    Duan Baoxing, Yang Yintang, Zhang Bo, Li Zhaoji

    J. Semicond.  2008, 29(4): 677

    Abstract PDF

    A novel Step Oxide-Bypassed (SOB) trench VDMOS structure is designed based on the Oxide-Bypassed concept proposed by Liang Y C.This structure is suitable for breakdown voltage below 300V to obtain ultra-low specific on-resistance.The main feature of this structure is the various thicknesses of sidewall oxide,which modulate electric field distribution in the drift region and the charge compensation effect.As a result,the breakdown voltage is increased no less than 20% due to the more uniform electric field of the drift region,while the specific on-resistance was reduced by 40%~60% for the step oxide bypassed compared with the oxide-bypassed structure.

  • A Novel Three-Section Self-Pulsating DFB Laser with Hybrid Grating

    Chen Dingbo, Zhu Hongliang, Liang Song, Wang Baojun, Wang Lufeng, Kong Duanhua, Zhang Wei, Wang Huan, Sun Yu, Zhang Yunxiao, Wang Liesong

    J. Semicond.  2008, 29(4): 682

    Abstract PDF

    A 1.55μm InGaAsP-InP three-section DFB laser with hybrid grating is fabricated and self-pulsations (SP) with frequencies around 20GHz are observed.The mechanism of SP generation in this device is researched.Furthermore,the important role of the phase tuning section on the SP is investigated.

  • A High Precision CMOS Opamp Suitable for ISFET Readout

    Zhang Chong, Yang Haigang, Wei Jinbao

    J. Semicond.  2008, 29(4): 686

    Abstract PDF

    This paper presents a high precision CMOS opamp suitable for ISFET readout.The opamp is tailored to provide a constant bias condition for ISFET as part of the readout circuits and,hence,is compatible for single chip integration with the sensor.A continuous time auto-zero stabilization technique is studied and employed,with the aim of suppressing the low frequency noises,including the offset voltage,1/f noise,and temperature drift.The design is based on a 0.35μm CMOS process.With a 3.3V power supply,it maintains a DC open loop gain of more than 100dB and an offset voltage of around 11μV,while the overall power dissipation is only 1.48mW.With this opamp,a pH microsensor is constructed,of which the functionality is verified by experimental tests.

  • A Hybrid Random Number Generator Using Single Electron Tunneling Junctions and MOS Transistors

    Zhang Wancheng, Wu Nanjian

    J. Semicond.  2008, 29(4): 693

    Abstract PDF

    This paper proposes a novel single electron random number generator (RNG).The generator consists of multiple tunneling junctions (MTJ) and a hybrid single electron transistor (SET)/MOS output circuit.It is an oscillator-based RNG.MTJ is used to implement a high-frequency oscillator,which uses the inherent physical randomness in tunneling events of the MTJ to achieve large frequency drift.The hybrid SET and MOS output circuit is used to amplify and buffer the output signal of the MTJ oscillator.The RNG circuit generates high-quality random digital sequences with a simple structure.The operation speed of this circuit is as high as 1GHz.The circuit also has good driven capability and low power dissipation.This novel random number generator is a promising device for future cryptographic systems and communication applications.

  • Design of a High Precision Array Pulse Sensor in TCM

    Huai Yongjin, Han Zhengsheng

    J. Semicond.  2008, 29(4): 701

    Abstract PDF

    We designed a high-precision array pulse sensor for TCM (traditional Chinese medicine) that can directly transform pulse-pressure signal into electric current signal and is compatible with CMOS technology.We adopted a sacrifice-layer craft for the transistor gate.During testing,we found that the precision of the capacitor for the array sensor is 0.5fF/hPa when the pressure was changing within the range of 1.5kPa to 9.5kPa.More importantly,the output-current and the pressure of the sensor have a good linearity and exponential characteristics.According to the data from the experiment,we conclude that the characteristic of the response-current is related to the area of the MOS gate.

  • Top-Down Design of 260k Color TFT-LCD One-Chip Driver ICs

    Wei Tingcun, Gao Wu

    J. Semicond.  2008, 29(4): 706

    Abstract PDF

    A top-down design methodology is proposed for the design of TFT-LCD one-chip driver ICs,and a 260k color,176RGB×220-dot TFT-LCD one-chip driver IC is successfully developed with silicon verification.This IC is a typical mixed-signal VLSI and is implemented by a 0.18μm HV CMOS process.The static power dissipation is about 5mW for 260k color display mode,and the settling time of the output grayscale voltages within 0.2% error is less than 26μs.

  • Design and Implementation of an FDP Chip

    Chen Liguang, Wang Yabin, Wu Fang, Lai Jinmei, Tong Jiarong, Zhang Huowen, Tu Rui, Wang Jian, Wang Yuan, Shen Qiushi, Yu Hui, Huang Junnai, Lu Haizhou, Pan Guanghua

    J. Semicond.  2008, 29(4): 713

    Abstract PDF

    A novel Fudan programmable logic chip (FDP) was designed and implemented with a SMIC 0.18μm CMOS logic process.The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT.The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly.The FDP contains 1,600 programmable logic cells,160 programmable I/O,and 16kbit dual port block RAM.Its die size is 6.104mm×6.620mm,with the package of QFP208.The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.

  • A Passive NCITS 256 UHF RFID Transponder

    Liu Zhongqi, Sun Xuguang, Bai Rongrong, Zhang Chun, Li Yongming, Wang Zhihua

    J. Semicond.  2008, 29(4): 719

    Abstract PDF

    This paper presents a passive UHF radio frequency identification (RFID) transponder with 2k bit standard commercial EEPROM in compliance with the NCITS 256 protocol.The communication range is 15m for the read operation and 0.3m for the write operation with 4W effective isotropic radiated power (EIRP) at 915MHz.The integrated IC is implemented in SMIC 0.18μm EEPROM CMOS technology.The die size is 1mm×1mm.The energy of the tag is harvested from RF electromagnetic waves transmitted by the reader with the help of a Schottky diode rectifier and achieves 25% power efficiency.

  • Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique

    Zhang Qingli, Wang Jinxiang, Yu Mingyan, Ye Yizheng

    J. Semicond.  2008, 29(4): 724

    Abstract PDF

    On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays.Thus,minimizing energy dissipation and propagation delay is an important design objective.In this paper,we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy.The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions.In the design process of applying encoding techniques for reduced bus delay and energy,we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length,which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints.This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.

  • Structural and Optical Properties of Amorphous MCT Films Deposited by RF Magnetron Sputtering

    Kong Jincheng, Kong Lingde, Zhao Jun, Zhang Pengju, Li Hongzhi, Li Xiongjun, Wang Shanli, Ji Rongbin

    J. Semicond.  2008, 29(4): 733

    Abstract PDF

    Amorphous HgCdTe(a-HgCdTe or a-MCT) films on glass substrate were deposited by RF magnetron sputtering technology.The amorphous structure of the MCT films were studied by XRD and AFM technology and the "growth window" of a-MCT was obtained.FTIR technology was used to study the optical properties of amorphous MCT films and the absorption coefficient of amorphous MCT films (~8E4cm-1) was obtained.We also observed three absorption regions near the optical gap of amorphous MCT.The optical gap of our a-MCT film is about 0.83eV.

  • Accurate Parameter Extraction of Substrate Resistance in an RF CMOS Model Valid up to 20GHz

    Zhao Yuhang, Hu Shaojian, Ren Zheng

    J. Semicond.  2008, 29(4): 737

    Abstract PDF

    An accurate method to extract substrate resistances of RF MOSFETs is proposed.The extraction method is based on equivalent circuit analysis for the PSP model.This method is experimentally validated on 90nm CMOS technology and predicts the output characteristics of MOSFETs accurately up to 20GHz.

  • An Analysis of the Importance of Recombination in the Base Side of the Emitter-Base SCR in Abrupt HBTs

    Zhou Shouli, Ren Xiaomin

    J. Semicond.  2008, 29(4): 741

    Abstract PDF

    In this paper,we investigate the importance of including recombination in the base side of the emitter-base space-charge-region(SCR) in the current continuity equation when computing the current gain in abrupt HBTs.Based on the thermionic field-diffusion model,new analytical expressions for the terminal currents are proposed.These new expressions are more accurate in predicting the performance of HBTs operating at high collector current density because of the inclusion of the recombination currents in the current continuity equation.

  • A Two-Dimensional Subthreshold Current Model for Dual Material Gate SOI nMOSFETs with Asymmetric Halos

    Luan Suzhen, Liu Hongxia, Jia Renxu, Wang Jin

    J. Semicond.  2008, 29(4): 746

    Abstract PDF

    A two-dimensional (2D) model for the subthreshold current in a dual-material gate silicon-on-insulator (SOI) MOSFET with a single halo is presented.The model considers a single halo doping in the channel near the source and a dual material gate to derive the channel potential using the explicit solution of the 2D Poisson’s equation.This,together with conventional drift-diffusion theory,results in the development of a subthreshold current model for the novel structure.Model verification is carried out using the 2D device simulator ISE.Good agreement is obtained between the model’s calculations and the simulated results.

  • Study of a New Pattern of Omni-Directional Reflector AlGaInP Thin-Film Light-Emitting Diodes

    Gao Wei, Zou Deshu, Li Jianjun, Guo Weiling, Shen Guangdi

    J. Semicond.  2008, 29(4): 751

    Abstract PDF

    A novel AlGaInP thin-film light emitting diode (LED) with an omni directional reflector structure is proposed and the corresponding fabrication process is developed.The omni-directional reflector was realized by the combination of a GaAs epi-wafer,SiO2 with conductive micro-contacts,and Au.The LED structure and Si substrate carrier were then brought into contact using silver-loaded epoxy.Then,the GaAs substrate was removed and stopped on the etching stop layer.After the etching stop layer was removed,a thin AuGeNi electrode,the roughed surface,an ITO current spreading layer,a thick AuGeNi n-electrode,a AuZnAu p-electrode,and alloy were fabricated.The wafer was cut into 300μm×300μm chips and then packaged into TO-18 without epoxy resin.For 20mA driving current,the voltage is 2.2V,and light intensity and light power respectively reach 195mcd and 3.78mW,which is 3.6 times higher than the absorbing-substrate LEDs.

  • Luminescence Characteristics of a Blue-Green Emission Thin Film Electroluminescence Device Based on a ZnSe Emitting Layer

    Jiang Weiwei, Zhao Suling, Zhang Fujun, Xu Zheng

    J. Semicond.  2008, 29(4): 754

    Abstract PDF

    A device with a ITO/SiO2/ZnSe/SiO2/Al structure was deposited by electron beam evaporation.Blue-green electroluminescence of ZnSe film,which does not appear in the traditional sandwich structure,was observed.The dependence of emission on applied voltage and frequency were studied in detail.The luminescence mechanism of the device was discussed.It is thought that original electrons are accelerated in the SiO2 layer where they obtain energy and bombard the ZnSe molecules.The electrons in the valence band of the ZnSe are excited to the conduction band.The excited electrons transit back to the valance band or the defect energy level and give emission.This mechanism is called solid state cathodoluminescence because the electrons accelerate in the solid but not in the vacuum.This phenomenon can provide a new way to realize blue inorganic electroluminescence.

  • Substrate Current and Hot-Carrier-Injection in High Voltage Asymmetrical n-Channel MOS Transistor Technology

    Dai Mingzhi, Liu Shaohua, Arthur Cheng, Li Hong, Andrew Yap, Wang Jun, Jiang Liu, Liao Kuanyang

    J. Semicond.  2008, 29(4): 757

    Abstract PDF

    The incorporation of high voltage transistors into the advanced VLSI chips has been limited by the reliability of the manufactured integrated circuits.As a monitor of hot-carrier-injection reliability,the substrate current (ISUB) usually increases in high voltage transistors,but has only one peak in standard low voltage transistors.Correspondingly,the mechanisms of the hot-carrier-injection effect in high voltage N-channel transistors should also be investigated.Based on the Poisson’s equation,and simulation and experimental results,a second impact ionization region is responsible for the second increase of ISUB.An explanation for the appearance of this second impact ionization region that differs from the prevalent theory,the Kirk-effect,is proposed.The Kirk-effect predicts that the typical high-electric field region widens from the gate edge to the n+ drain edge.However,two separate high-electric-field regions with fixed locations coexist instead.The second high-field region is not the expansion of the conventional region.An improved equation for ISUB is proposed according to the two-high-field-region model.This two-high-field-region model is also consistent with the phenomena observed under the various HCI stress conditions with and without back bias.Back bias reduces the supplied voltage for high-voltage transistors by half without degrading their performance and reliability.

  • Electrically Confined Aperture Formed by Ion Implantation and Its Effect on Device Optoelectronic Characteristics

    Liu Cheng, Cao Chunfang, Lao Yanfeng, Cao Meng, Wu Huizhen

    J. Semicond.  2008, 29(4): 765

    Abstract PDF

    1.3μm surface-emitting electroluminescence (EL) device structures are fabricated.The electrically confined apertures are formed by ion implantation and thermal annealing technology.By studying electrical and optical characteristics of the device structure,we found that the optimized thermal annealing temperature is 450℃ when the ion implantation dose is 5E14cm-2.The resistance of the device structure linearly increases with the decrease of aperture diameters.EL spectra intensities are remarkably enhanced after the electrically confined aperture is formed.For instance,the intensity of the sample with 15μm aperture is 4 times that without aperture.Finally,the effects of the electrically confined aperture on the EL spectra of the structure are physically explained.

  • Charge Storage Characteristics of Nonvolatile Floating-Gate Memory Based on Gradual Ge1-xSix/Si Heteronanocrystals

    Lü Jin, Chen Yubin, Zuo Zheng, Shi Yi, Pu Lin, Zheng Youdou

    J. Semicond.  2008, 29(4): 770

    Abstract PDF

    Gradual Ge1-xSix/Si hetero-nanocrystals on ultrathin SiO2 layers were fabricated by combining self-assembled growth and the selective chemical etching method.Charge storage characteristics of nonvolatile floating-gate memory based on gradual Ge1-xSix/Si hetero-nanocrystals have been fabricated and investigated through capacitance-voltage (C-V) and capacitance-time (C-t) measurements.The findings indicate that holes reach a longer retention time in gradual Ge1-xSix/Si hetero-nanocrystals,which can be attributed to the holes trapped solidly on the side of the higher valence band of the compound potential barrier caused by the offset between Ge and Si.

  • Effects of the Anodic Alumina Substrate Fabrication Process on a Ta-N Thin Film Integrated Resistor

    Zhu Dapeng, Luo Le

    J. Semicond.  2008, 29(4): 774

    Abstract PDF

    A Ta-N thin film resistor was integrated in anodic alumina MCM-D substrate using RF reactive sputtering.The effects of the aluminum anodization process on the microstructure of the Ta-N resistor were studied.The results show that the oxide bulges composed of Ta2O5 and Ta-O-N were formed at the surface of Ta-N film due to the effect of the upper layer of porous anodic alumina.The oxide bulge thickness was related to the anodiztion voltage.The resistivity and TCR of the remaining Ta-N resistor remained unchanged.The resistor was more stable because of the protection of the oxide bulges.

  • Analysis of Processing Chamber Flow Field Characteristics for an ICP Etcher Based on Regression Orthogonal Design

    Cheng Jia, Zhu Yu, Duan Guanghong, Wang Chunhong

    J. Semicond.  2008, 29(4): 780

    Abstract PDF

    We attempt to investigate the influence of the processing chamber configuration of an inductively coupled plasma (ICP) etcher on flow field characteristics.Four parameters,including chamber radius,chamber height,inlet radius,and inlet mass flow,are arranged regression orthogonally to study the two-dimensional flow field models of the processing chamber of the ICP etcher,which was built in the commercial software,CFD-ACE+.A function is defined to evaluate the uniformity of the pressure distribution above the electrostatic chuck.The quantificational relation between key parameters and the uniformity of pressure distribution was found through regression analysis of experimental results,and,furthermore,a quadric regression equation with high fitting degree was determined.The result demonstrates that the chamber height is the most significant factor.The results from the regression equation agree well with those from simulation.This research can provide insight into the study and design configuration of etchers,chemical vapor deposition (CVD) equipment,and oxidation/diffusion systems that are similar in configuration and processing condition.

  • An Energy Band Design for p-Type Tensile Strained Si/SiGe Quantum Well Infrared Photodetectors

    Deng Heqing, Lin Guijiang, Lai Hongkai, Li Cheng, Chen Songyan, Yu Jinzhong

    J. Semicond.  2008, 29(4): 785

    Abstract PDF

    Quantum well infrared photodetectors (QWIPs) offer numerous potential applications for defense,industry,and medicine.A novel p-type tensile strained Si/SiGe QWIP is proposed in this paper.The valence band structure of the strained Si/SiGe quantum well and hole effective mass of the strained SiGe alloy are calculated using the k·p method.When tensile strain is induced in the quantum wells,the light-hole state with small effective mass becomes the ground state,which is expected to have lower dark current than n-type QWIPs and also have larger absorption coefficient and better transport characteristics than conventional unstrained or compressive strained p-type QWIPs.Designs for p-type tensile strained Si/SiGe QWIP based on the bound-to-quasi-bound transitions are also discussed.

  • Optimization of a Thermoelectric Microwave Power Sensor

    Han Lei, Huang Qing’an, Liao Xiaoping

    J. Semicond.  2008, 29(4): 789

    Abstract PDF

    A 2D analytical model of the thermal distribution of a thermoelectric microwave power sensor is presented.In order to optimize the size of the sensor,the influences of various structure parameters on the thermal distribution are analyzed.The paper presents the design principle of the parameters,including the membrane thickness,the distance between the matched resistor and the hot junctions of the thermopile,and the suspended length of the thermopile,to achieve high sensitivity.The analytical results agree well with the Ansys simulative results.

  • A "Time Reuse" Technique for Design of a Low-Power,High-Speed Multi-Modulus Divider in a Frequency Synthesizer

    Yuan Quan, Yang Haigang, Dong Fangyuan, Zhong Lungui

    J. Semicond.  2008, 29(4): 794

    Abstract PDF

    A low power,continuous phase-switching multi-modulus divider is proposed based on the "time reuse" method.The novel phase-switching control strategy significantly reduces the delay of the phase-switching control loop so that the multi-modulus divider can work with higher input frequency and obtain the maximum modulus for a low power supply.According to the measurement results,this multi-modulus divider can divide the 2.4GHz input frequency by 48 up to 64 for a minimum power supply voltage of 2.5V in a 0.35μm CMOS process.The maximum power dissipation is only 4.85mW.Compared with other CMOS multi-modulus dividers reported recently,our design demonstrates a considerable improvement in the power-to-speed ratio.

  • A CMOS Down-Converting Mixer For OFDM UWB Receivers

    Hu Jiasheng, Li Wei, Li Ning

    J. Semicond.  2008, 29(4): 800

    Abstract PDF

    A down-converting mixer fabricated with 0.18μm RF CMOS technology is designed for OFDM-UWB applications.Differing from conventional Gilbert cell topology,a differential topology is proposed and applied in order to reduce the noise contribution and disturbance from the large signal of the local oscillation,as well as to lower the DC consumption of the mixer.The test result demonstrates that over the intermediate frequency band of 4~252MHz,the mixer achieves conversion gain of above 2.5~7.8dB,NF of 22.5~26dB,isolation among the ports of about -50dB,and consumes about 8mA under a 1.8V supply.

  • Research and Implementation Process of a 42" PDP Scan Driver IC

    Hong Hui, Han Yan, Han Chenggong, Wang Yalin

    J. Semicond.  2008, 29(4): 806

    Abstract PDF

    Based on independent research of bipolar-CMOS-DMOS high voltage processes,a new plasma display panel scan driver IC for 42" digital TVs is implemented.The high voltage power devices are integrated and compatible with ordinary CMOS and Bipolar devices and work in low voltage.The level-shifter driver circuit matches this process perfectly,which greatly enhances its performance and reduces the chip size.The test results show that the performance of this PDP scan driver IC is perfect and its technical parameters achieve the same level as those of foreign products.It fully satisfies the demands of the 42" PDP system under the condition of a low power supply of 5V and a high power supply of 160V .


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