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Volume 28, Issue 3, Mar 2007

    LETTERS

  • Hydrogenation of Polycrystalline SiGe Thin Films by Hot Wire Technique

    Zhang Jianjun, Hu Zengxin, Gu Shibin, Zhao Ying, Geng Xinhua

    Chin. J. Semicond.  2007, 28(3): 317

    Abstract PDF

    An optimized condition for defect passivation by the hot-wire technique was established.Effects of hydrogenation for polycrystalline SiGe (poly-Si1-xGex) thin films were estimated by investigating the dark conductivity and activation energy that derive from the conductivity as a function of the temperature.The results show that this technique can effectively reduce defects present in poly-Si1-xGex films.By optimizing the substrate and filament temperatures,the treatment can be accomplished in a short time of 20~30min,which is considerably shorter than other hydrogenation techniques.

  • Effects of Si Ion Implantation on the Total-Dose Radiation Properties of SIMOX SOI Materials

    Yang Hui, Zhang Enxia, Zhang Zhengxuan

    Chin. J. Semicond.  2007, 28(3): 323

    Abstract PDF

    To improve the total-dose radiation hardness,silicon-on-insulator (SOI) wafers fabricated by the separation-by-implanted-oxygen (SIMOX) method are modified by Si ion implantation into the buried oxide with a post anneal.The ID-VG characteristics can be tested with the pseudo-MOSFET method before and after radiation.The results show that a proper Si-ion-implantation method can enhance the total-dose radiation tolerance of the materials.

  • Dual Material Gate SOI MOSFET with a Single Halo

    Li Zunchao, Jiang Yaolin, Wu Jianmin

    Chin. J. Semicond.  2007, 28(3): 327

    Abstract PDF

    In order to suppress drain-induced barrier lowering in dual material gate SOI MOSFETs,halo doping is used in the channel near the source.Two-dimensional analytical models of surface potential and threshold voltage for the novel SOI MOSFET are developed based on the explicit solution of the two-dimensional Poisson’s equation.Its characteristic improvement is investigated.It is concluded that the novel structure exhibits better suppression of drain-induced barrier lowering and higher carrier transport efficiency than conventional dual material gate SOI MOSFETs.Its drain-induced barrier lowering decreases with increasing halo doping concentration but does not change monotonically with halo length.The analytical models agree well with the two-dimensional device simulator MEDICI.

  • A Monolithic Integrated Logic Circuit of Resonant Tunneling Diodes and a HEMT

    Dai Yang, Huang Yinglong, Liu Wei, Ma Long, Yang Fuhua, Wang Liangchen, Zeng Yiping, Zheng Houzhi

    Chin. J. Semicond.  2007, 28(3): 332

    Abstract PDF

    A technology for the monolithic integration of resonant tunneling diodes (RTDs) and high electron mobility transistors (HEMTs) is developed.Molecular beam epitaxy is used to grow an RTD on a HEMT structure on GaAs substrate.The RTD has a room temperature peak-to-valley ratio of 5.2∶1 with a peak current density of 22.5kA/cm2.The HEMT has a 1μm gate length with a -1V threshold voltage.A logic circuit called a monostable-to-bistable transition logic element (MOBILE) circuit is developed.The experimental result confirms that the fabricated logic circuit operates successfully with frequency operations of up to 2GHz.

  • A Novel Low Power ASK Receiver with AGC Loop

    Yao Jinke, Chi Baoyong, Wang Zhihua

    Chin. J. Semicond.  2007, 28(3): 337

    Abstract PDF

    We report a low power ASK IF receiver for short-range wireless systems,which includes an AGC loop that compensates the channel attenuation and an ASK detector.A novel current-limited transconductor and feed-forward differential peak detector have been designed to maintain a high compression ratio and fast response for the AGC with lower power consumption.A storage unit with a zero and a feed-forward structure have been introduced into the peak detector to control the damping characteristic of the AGC loop.A rectifier and low-pass filter included in the ASK detector have been integrated into a more compact structure to further lower the power consumption.The simulation results show the feasibility of the proposed technique.

  • PAPERS

  • A Novel Ideal Ohmic Contact SiGeC/Si Power Diode with Graded Doping Concentration

    Liu Jing, Gao Yong, Yang Yuan, Wang Cailin

    Chin. J. Semicond.  2007, 28(3): 342

    Abstract PDF

    A novel structure of ideal ohmic contact p+(SiGeC)-n--n+ diodes with three-step graded doping concentration in the base region is presented,and the changing doping concentration gradient is also optimized.Using MEDICI,the physical parameter models applicable for SiGeC/Si heterojunction power diodes are given.The simulation results indicate that the diodes with graded doping concentration in the base region not only have the merit of fast and soft reverse recovery but also double reverse blocking voltage,and their forward conducting voltage has dropped to some extent,compared to the diodes with constant doping concentration in the base region.The new structure achieves a good trade-off in Qs-Vf-Ir,and its combination of properties is superior to ideal ohmic contact diodes and conventional diodes.

  • Effect of Snapback Stress on Gate Oxide Integrity of nMOSFET in 90nm Technology

    Zhu Zhiwei, Hao Yue, Ma Xiaohua

    Chin. J. Semicond.  2007, 28(3): 349

    Abstract PDF

    By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress.The damage incurred during stress causes device degradation that follows an approximate power law with stress time.Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd (charge to breakdown),and it may also cause the degradation of off-state drain leakage current.Stress-induced gate oxide damage is located not only in the drain side but also in the source side.The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.

  • Realizing High Breakdown Voltage SJ-LDMOS on Bulk Silicon Using a Partial n-Buried Layer

    Chen Wanjun, Zhang Bo, Li Zhaoji

    Chin. J. Semicond.  2007, 28(3): 355

    Abstract PDF

    A new design concept is proposed to eliminate the substrate-assisted depletion effect that significantly degrades the breakdown voltage (BV) of conventional super junction-LDMOS.The key feature of the new concept is that a partial buried layer is implemented which compensates for the charge interaction between the p-substrate and SJ region,realizing high breakdown voltage and low on-resistance.Numerical simulation results indicate that the proposed device features high breakdown voltage,low on-resistance,and reduced sensitivity to doping imbalance in the pillars.In addition,the proposed device is compatible with smart power technology.

  • Abstraction of Small Signal Equivalent Circuit Parameters of Enhancement-Mode InGaP/AlGaAs/InGaAs PHEMT

    Xu Jingbo, Yin Junjian, Zhang Haiying, Li Xiao, Liu Liang, Ye Tianchun

    Chin. J. Semicond.  2007, 28(3): 361

    Abstract PDF

    An extraction method of the component parameter values of an enhancement-mode InGaP/AlGaAs/InGaAs PHEMT small signal equivalent circuit is presented,and these component parameter values are extracted by using the EEHEMT1 model of IC-CAP software.The extraction results are verified by ADS software,and the DC I-V curves and S parameters simulated by ADS are basically accordant with those of the test results.These results indicate that the EEHEMT1 model can be used for extracting the component parameters of an enhancement-mode PHEMT.

  • A Fast Acquisition PLL with Wide Tuning Range

    Ge Yan, Jia Song, Ye Hongfei, Ji Lijiu

    Chin. J. Semicond.  2007, 28(3): 365

    Abstract PDF

    We present a design for an adaptive gain phase-locked loop (PLL) that features fast acquisition,low jitter,and wide tuning range.A dual-edge-triggered phase frequency detector (PFD) and a self-regulated voltage controlled oscillator (VCO) are employed in this design to realize the aforementioned properties.Measured results show that the experimental chip,implemented in a standard 0.5μm 5V CMOS logic process,has an acquisition time of about 150ns at 37% frequency variation and an output RMS jitter of 39ps at 640MHz.

  • A Highly Linear Filter and VGA with DC-Offset Correctionfor GSM/WCDMA Receivers

    Zhou Zhujin, Li Zhisheng, Li Ning, Li Wei, Ren Junyan

    Chin. J. Semicond.  2007, 28(3): 372

    Abstract PDF

    This paper describes a complete baseband chain for both GSM and WCDMA receivers with a SMIC 0.35μm mixed signal process.The chain consists of a dual-mode,highly linear,fourth order Chebyshev active RC filter and three VGA stages.The filter is designed to meet the bandwidth specifications of the GSM and WCDMA standards and share the maximum number of components between the two modes to reduce manufacturing cost.The design is free of DC-offset and has an inter-stage high-pass filter,and operational amplifiers with adjustable GBW are used to minimize GSM-mode power consumption.The measured noise figures are 27.3 and 42dBm in WCDMA and GSM modes,respectively,at the maximum gain.The IIP3 is 40dBm at unit gain in the WCDMA mode,and the circuit consumes 47.0mW.The IIP3 is 28dBm in the GSM mode,and the circuit consumes 31.8mW.The supply voltage is 3.3V.

  • An Analog Equalizer and Baseline-Wander Cancellerfor 100/1000Base-TX Transceiver

    Chen Haoqiong, Li Xuechu, Xu Changxi, Niu Wencheng

    Chin. J. Semicond.  2007, 28(3): 377

    Abstract PDF

    A frequency-domain equalizer with a mixed-signal adaptive control loop and a novel baseline wander (BLW) canceller are proposed.The equalizer is independent of channel-modeling accuracy,and its control loop is intrinsically stable.An AGC function is incorporated into the equalizer without an extra AGC circuit.The proposed BLW canceller uses a peak detector to monitor the BLW and full feedback method to accomplish BLW canceling.High canceling accuracy and robust performance are achieved.The circuits are tested in 0.25μm CMOS technology.Better performance and smaller silicon area are achieved compared with results in the literature.

  • Two-Stage Driving Circuit for One-Chip TFT-LCD Driver IC

    Gao Wu, Wei Tingcun, Gao Deyuan

    Chin. J. Semicond.  2007, 28(3): 385

    Abstract PDF

    A two-stage driving circuit of a one-chip TFT-LCD driver IC for portable electronic devices is proposed.The driving buffers of the new circuit are built in the γ-correction circuit rather than in the source driver.The power consumption,die area,and driving capability of the driving circuit are discussed in detail.For a two-stage driving circuit with 13 driving buffers,the settling time of the driving voltage within 0.2% error is about 19.2μs when 396 pixel-loads are driven by the same grayscale voltage.The quiescent current of the whole driving circuit is 518μA,and the power consumption can be reduced by 77%.The proposed driving circuit is successfully applied in a 132RGB×176-dot,260k color one-chip driver IC developed by us for the TFT-LCD of mobile phone,and it can also be used in other portable electronic devices, such as PDAs and digital cameras.

  • Low-Power CMOS IC for Function Electrical Stimulation of Nerves

    Li Wenyuan, Wang Zhigong,

    Chin. J. Semicond.  2007, 28(3): 393

    Abstract PDF

    A low-power IC for function electrical stimulation (FES) of nerves is designed for an implantable system and fabricated in CSMC’s 0.6μm CMOS technology.The IC can be used for stimulating animals’ spinal nerve bundles and other nerves connected with a cuff type electrode.It consists of a pre-amplifier,a main amplifier,and an output stage.According to the neural signal spectrum,the bandwidth of the FES signal generator circuit is defined from 1Hz to 400kHz.The gain of the circuit is about 66dB with an output impedance of 90Ω.The IC can function under a single supply voltage of 3~5V.A rail-to-rail output stage helps to use the coupled power efficiently.The measured time domain performance shows that the bandwidth and the gain of the IC agree with the design.The power consumption is lower than 6mW.

  • An AND-LUT Based Hybrid FPGA Architecture

    Chen Liguang, Lai Jinmei, Tong Jiarong

    Chin. J. Semicond.  2007, 28(3): 398

    Abstract PDF

    A new hybrid FPGA architecture is proposed.The logic tile,which consists of a logic cluster and related connection boxes (CBs),can be configured as either programmable logic arrays (PLAs) or look-up tables (LUTs).This architecture can be classified as an AND-LUT array.PLAs are suitable for the implementation of high fan-in logic circuits,while LUTs are used to implement low fan-in logic circuits.As a result,the proposed hybrid FPGA architecture (HFA) is more flexible to improve logic density.Experiments based on MCNC benchmark circuits were performed in both the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption.Preliminary results indicate that on average,the area is reduced by 46% using the new hybrid architecture.

  • Dynamic Behavior of Excitons in Coupled Double Quantum Dots Driven by DC-AC Electric Fields

    Su Xiyu, Quan Xiumei, Guo Dejun

    Chin. J. Semicond.  2007, 28(3): 404

    Abstract PDF

    With a two-site Hubbard model and the Floquet theory,the dynamic behavior of excitons in coupled double quantum dots driven by DC-AC electric fields is investigated.The time-dependent Schrdinger equation is numerically solved,and Pmin,the minimum probability for the electron and the hole to remain in the initial localized state within 20 periods of the external field,is given.Results show that for a weak field,the exciton mainly oscillates between two localized states;however,for a strong field,the electron and the hole can independently tunnel between the two quantum dots.The driving field tends to drive the electron and the hole apart,and under appropriate conditions they can be localized in the initial state for a short time.The DC field breaks the dynamic symmetry of the system and affects the dynamic localization.

  • XPS of SiCN Thin Films Prepared by C+ Implantation in Amorphous SiNx∶H

    Chen Chao, Liu Yuzhen, Dong Lijun, Chen Dapeng, Wang Xiaobo

    Chin. J. Semicond.  2007, 28(3): 415

    Abstract PDF

    This paper reports an experimental procedure to analyze the properties of SiCN films.Hydrogenated amorphous silicon nitride films (a-SiNx∶H) were implanted with 30keV C+ with a doping dose of 2e17cm-2 at room temperature.The composition,structure,and bonding structure of SiCN films treated by thermal annealing for 2h at 800℃ were analyzed with X-ray photoelectron spectroscopy (XPS),Auger electron spectroscopy (AES),and Raman spectroscopy.SiCN films that exhibit complicated bond structures with carbon content up to 45%~50% can be determined by AES.In addition,the C concentration varies with the depth and shows two distributions.Furthermore,a typical XPS spectrum showing the C-Si,CN,and Si-N bonds demonstrates that the films after 800℃ thermal annealing for 2h are composed of two structures at different depths,one is SiC and SiNx,and the other is SiCxNy.In summary,the existence of the ternary SiCN can be observed with reasonable silicon content at appropriate annealing temperatures.These experimental results may provide information about the possibility and conditions of growing SiCN films,and they may get important application in future engineering practices.

  • Thermal Conductivity of Meso-Porous Silicon Prepared by the Double-Tank Electrochemical Corrosion Method

    Fang Zhenqian, Hu Ming, Zhang Wei, Zhang Xurui, Yang Haibo

    Chin. J. Semicond.  2007, 28(3): 420

    Abstract PDF

    A theoretical model describing mechanisms of heat transfer in meso-porous silicon (meso-PS) layer based on the effective medium theory is brought forward.The influencing factors of effective thermal conductivity (ETC) of meso-PS,including the porosity of meso-PS,the heat capacity of silicon at constant volume,and the phonon mean free path of silicon,were analyzed theoretically,and a calculation formula of TC of meso-PS was given.The porosities of meso-PS samples prepared by the double-tank electrochemical corrosion method were 62% and 79%, respectively.Their TC values yielded by micro-Raman spectroscopy were 8.315 and 0.949W/(m·K),respectively.Scanning electron microscopy shows that the average characteristic sizes of meso-PS samples with porosities of 62% and 79% are 10 and 5nm,respectively.According to the formula for TC of meso-PS,the theoretical ETC value of a meso-PS layer with a porosity of 62% and an average characteristic size of 10nm is 10.753 W/(m·K),and that of meso-PS layer with a porosity of 79% and an average characteristic size of 5nm is 1.035W/(m·K).It is shown that the theoretical values are quite in good agreement with experimental data.Meso-PS with low TC is well suited for thermal insulation material,which is attractive for use in microsensors and microelectro-mechanical systems.

  • Deposition of Al-N Co-Doped p-Type Zn0.95Mg0.05O Thin Films

    Jian Zhongxiang, Ye Zhizhen, Gao Guohua, Lu Yangfan, Zhao Binghui, Zeng Yujia, Zhu Liping

    Chin. J. Semicond.  2007, 28(3): 425

    Abstract PDF

    Al-N codoped p-type Zn0.95Mg0.05O thin films were deposited on glass substrates by DC reactive manetron sputtering, N2O was used as the N doping source. The XRD patterns showed that the introduction of Mg and Al has no effect on the crystallinity of the films, the films all showed c-axis preferential orientation.A conversion of conduction type was confirmed by Hall effect measurement in a range of temperature from 400 to 530℃.The lowest reliable room temperature resistivity was found to be 58.5Ω·cm,with a carrier concentration of 1.95e17cm-3 and a Hall mobility of 0.546cm2/(V·s).The p-type behavior is stable.The optical transmittance spectra reveal blue shift in optical bandgap for the p-type Zn0.95Mg0.05O comparing with that for pure ZnO,which confirms the effective incorporation of Mg.The band gap of alloy is controllable.

  • Effects of Oxygen Source Ionization on the Growth and Properties of MOCVD ZnO Material

    Li Feng, Gu Shulin, Ye Jiandong, Zhu Shunming, Zhang Rong, Zheng Youdou

    Chin. J. Semicond.  2007, 28(3): 430

    Abstract PDF

    ZnO thin films were deposited with low-pressure MOCVD at different substrate temperatures.The effects of oxygen source ionization on the growth and properties of MOCVD ZnO material were investigated.The crystal structure and surface morphology of ZnO films were characterized by X-ray diffraction and atomic force microscopy,respectively.Room temperature and low temperature photoluminescence were used to investigate the optical properties of ZnO.It was found that the ionization of the oxygen source has a marked influence on the growth rate,crystal orientation,surface morphology,and other properties

  • Mo/Schottky Barrier Diodes on 4H-Silicon Carbide

    Zhang Fasheng, Li Xinran

    Chin. J. Semicond.  2007, 28(3): 435

    Abstract PDF

    With microelectronics plane technology,RF sputtering was used to deposit Mo to form a Schottky contact and electron beam evaporation was used to deposit Ni to form an ohmic contact in high vacuum ambient,and Mo/4H-SiC Schottky-barrier diodes were made in structures containing three-FLR.High-temperature annealing for the Mo contact is found to be effective in controlling the Schottky-barrier height at 1.2~1.3eV without degradation of the n-factor and reverse characteristics.A breakdown voltage of 3kV,a specific on resistance of 9.2mΩ·cm2, and a good V2b/Ron value of 978MW/cm2 for Mo/4H-SiC Schottky-barrier diodes are obtained experimentally.

  • Large Signal Modeling of GaAs HFET/PHEMT

    Zhang Shujing, Yang Ruixia, Gao Xuebang, Yang Kewu

    Chin. J. Semicond.  2007, 28(3): 439

    Abstract PDF

    The large-signal modeling of a GaAs HFET/PHEMT is the key of designing a microwave integrated power amplifier.Through analyzing the modeling design,calibrating it on-wafer,and applying appropriate measurement techniques,we develop a modified charge conservation EEHEMT1 model.This is accomplished by using modified Cold FET measurement technology and adopting the testing technique on-wafer and combining it with narrow pulse testing technology.The experimental results agree closely with simulated results.

  • Analysis of the Fabrication of a Surface Emitting Laser by the Bonding Method

    He Guorong, Zheng Wanhua, Qu Hongwei, Yang Guohua, Wang Qing, Wu Xuming, Cao Yulian, Chen Lianghui

    Chin. J. Semicond.  2007, 28(3): 444

    Abstract PDF

    InGaAsP/InP active regions were single-fused or double-fused to GaAs/AlAs DBRs by hydrophobic bonding.The mechanical,optical,and electrical characteristics of the bonded interfaces were investigated through SEM,reflection spectrum,PL spectrum,and I-Vcurves.Good performance indicates an excellent interface.This makes it possible for the fabrication of long-wavelength surface emitting lasers by the bonding technique.

  • Application of "Flow-Graph" Technique in Measurement Calibration of High Frequency Characteristics of Photodetectors

    Miao Ang, Huang Yongqing, Li Yiqun, Wu Qiang, Huang Hui, Ren Xiaomin

    Chin. J. Semicond.  2007, 28(3): 448

    Abstract PDF

    In order to reduce the inaccuracy of traditional calibration,the "flow-graph" method is proposed.This method takes into account the effects of the inaccuracy of various frequency responses and the mismatch between different ports.Furthermore,a calibration formula is deduced.This method was applied to the further calibration analysis of a typical lightwave component analyzer (LCA)-based photodetector measurement system.The experiment of a novel photodetector demonstrates that in the range of 130MHz to 20GHz,an obvious improvement in the calibration of theS21 parameter has been achieved compared to the traditional algorithm,and the proposed method is proved feasible.

  • 2.5Gbps/ch 2-Channel Parallel Clock and Data Recovery Circuit

    Liu Yongwang, Wang Zhigong, Li Wei

    Chin. J. Semicond.  2007, 28(3): 460

    Abstract PDF

    A monolithic 2.5Gbps/ch 2-channel parallel clock and data recovery circuit is designed and fabricated in TSMC’s standard 0.18μm CMOS process.PLL and DLL techniques are applied to implement the IC.Compared with conventional circuits,the recovered parallel data is bit-synchronous,and the reference clock is avoided.The rms jitter of the recovered clock is 2.6ps for 2 parallel PRBS input data (231-1).The rms jitters of the two recovered data are 3.3 and 3.4ps,respectively.

  • Criterion of Microroughness for Self-Propagating Wafer Bonding

    Ma Ziwen, Tang Zirong, Liao Guanglan, Shi Tielin

    Chin. J. Semicond.  2007, 28(3): 465

    Abstract PDF

    The criterion of microroughness for self-propagating wafer bonding is studied according to JKR contact theory, where the microroughness model is based on a sinusoidal distribution for gap height and gap length. Our analysis shows that the criterion for self-propagating wafer bonding is relevant to the dimensionless parameter.In silicon wafer bonding, using the dimensionless parameter as a measure,three regions of silicon wafer bonding can be identified:self-propagating silicon wafer bonding (α>1.065),external pressure assisted silicon wafer bonding (0.57<α<1.065), and silicon wafer bonding with voids (α<0.57).Experimental data are in reasonable agreement with this theory.

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