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Volume 26, Issue 10, Oct 2005

    CONTENTS

  • X-Band GaN Power HEMTs with Power Density of 2.23W/mm Grown on Sapphire by MOCVD

    Wang Xiaoliang, Liu Xinyu, Hu Guoxin, Wang Junxi, Ma Zhiyong, Wang Cuimei, Li Jianping, Ran Junxue, Zheng Yingkui, Qian He, Zeng Y

    Chin. J. Semicond.  2005, 26(10): 1865

    Abstract PDF

    The growth,fabrication,and characterization of 0.2μm gate-length AlGaN/GaN HEMTs, with a high mobility GaN thin layer as a channel,grown on (0001) sapphire substrates by MOCVD,are described.The unintentionally doped 2.5μm thick GaN epilayers grown with the same conditions as the GaN channel have a room temperature electron mobility of 741cm2/(V·s) at an electron concentration of 1.52e16cm-3.The resistivity of the thick GaN buffer layer is greater than 1e8Ω·cm at room temperature.The 50mm HEMT wafers grown on sapphire substrates show an average sheet resistance of 440.9Ω/□ with uniformity better than 96%.Devices of 0.2μm×40μm gate periphery exhibit a maximum extrinsic transconductance of 250mS/mm and a current gain cutoff frequency of 77GHz.The AlGaN/GaN HEMTs with 0.8mm gate width display a total output power of 1.78W (2.23W/mm) and a linear gain of 13.3dB at 8GHz.The power devices also show a saturated current density as high as 1.07A/mm at a gate bias of 0.5V.

  • A DBRTD with a High PVCR and a Peak Current Density at Room Temperature

    Yili Chengrong, Xie Changqing, Wang Congshun, Liu Ming, and Ye Tianchun

    Chin. J. Semicond.  2005, 26(10): 1871

    Abstract PDF

    AlAs/GaAs/In0.1Ga0.9As/GaAs/AlAs double-barrier resonant tunneling diodes(DBRTDs) grown on a semi-insulated GaAs substrate with molecular beam epitaxy is demonstrated.By sandwiching the In0.1Ga0.9As layer between GaAs layers,potential wells beside the two sides of barrier are deepened,resulting in an increase of the peak-to-valley current ratio (PVCR) and a peak current density.A special shape of collector is designed in order to reduce contact resistance and non-uniformity of the current;as a result the total current density in the device is increased.The use of thin barriers is also helpful for the improvement of the PVCR and the peak current density in DBRTDs.The devices exhibit a maximum PVCR of 13.98 and a peak current density of 89kA/cm2 at room temperature.

  • Improved Breakdown Voltage of Partially Depleted SOI nMOSFETs with Half-Back-Channel Implantation

    Wu Junfeng, Zhong Xinghua, Li Duoli, Bi Jinshun, and Hai Chaohe

    Chin. J. Semicond.  2005, 26(10): 1875

    Abstract PDF

    :FB (floating-body) and BC (body-contact) partially depleted SOI nMOSFETs with HBC(half-back-channel) implantation are fabricated.Test results show that such devices have good performance in delaying the occurrence of the "kink" phenomenon and improving the breakdown voltage as compared to conventional PDSOI nMOSFETs,while not decreasing the threshold voltage of the back gate obviously.Numerical simulation shows that a reduced electrical field in the drain contributes to the improvement of the breakdown voltage and a delay of the "kink" effect.A detailed analysis is given for the cause of such improvement of breakdown voltage and the delay of the "kink" effect.

  • 20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS

    Wang Gui, Wang Zhigong, Wang Huan, Ding Jingfeng, and Xiong Mingzhen

    Chin. J. Semicond.  2005, 26(10): 1881

    Abstract PDF

    A 1∶2 demultiplexer is designed and realized in standard 0.18μm CMOS technology.A novel high-speed and low-voltage latch is used to realize the core circuit cell.Compared to the traditional source-coupled FET logic structure latch,its power supply voltage is lower and the speed is faster.In addition,the negative feedback is used in the buffer circuit to widen its bandwidth.Measurement results show that the chip can work at the data rate of 20Gb/s.The supply voltage is 1.8V and the current, including the buffer circuit,is 72mA.

  • An Improved Charge Pumping Method to Study Distribution of Trapped Charges in SONOS Memory

    Sun Lei, Pang Huiqing, Pan Liyang, and Zhu Jun

    Chin. J. Semicond.  2005, 26(10): 1886

    Abstract PDF

    In silicon-oxide-nitride-oxide-silicon (SONOS) memory and other charge trapping memories,the charge distribution after programming operation has great impact on the device’s characteristics,such as reading,programming/erasing,and reliability.The lateral distribution of injected charges can be measured precisely using the charge pumping method.To improve the precision of the actual measurement,a combination of a constant low voltage method and a constant high voltage method is introduced during the charge pumping testing of the drain side and the source side,respectively.Finally,the electron distribution after channel hot electron programming in SONOS memory is obtained,which is close to the drain side with a width of about 50nm.

  • A Linear CMOS OTA and Its Application to a 3.3V 20MHz High-Q gm-C Bandpass Filter

    Wang, Bin, and, Yang, Huazhong

    Chin. J. Semicond.  2005, 26(10): 1892

    Abstract PDF

    A design of a linear and fully-balanced operational transconductance amplifier (OTA) with improved high DC gain and wide bandwidth is presented.Derivative from a single common-source field effect transistor (FET) cascade and its DC I-V characteristics,the third-order coefficient g3 has been well compensated with a parallel FET operated in the triode region,which has even-odd symmetries between the boundary of the saturation and triode region.Therefore,for high linearity,a simple solution is obtained to increase input signal amplitude in saturation for the application of OTA continuous-time filters.A negative resistance load (NRL) technique is used for the compensation of parasitic output resistance and an achievement of a high DC-gain of the OTA circuits without extra internal nodes.Additionally,derivations from the ideal -90. phase of the gm-C integrator mainly due to a finite DC gain and parasitic poles will be avoided in the frequency range of interest.HSPICE simulation shows that the total harmonic distortion at 1Vp-p is less than 1% from a single 3.3V supply.As an application of the VHF CMOS OTA,a second-order OTA-C bandpass filter is fabricated using a 0.18μm CMOS process with two kinds of gate-oxide layers,which has achieved a center frequency of 20MHz,a 3dB-bandwidth of 180kHz,and a quality factor of 110.

  • Theoretical Analysis of Gain and Threshold Current Density for Long Wavelength GaAs-Based Quantum-Dot Lasers

    Deng Shengling, Huang Yongzhen, Jin Chaoyuan, and Yu Lijuan

    Chin. J. Semicond.  2005, 26(10): 1898

    Abstract PDF

    Quantum dot gain spectra based on harmonic oscillator model are calculated including and excluding excitons.The effects of non-equilibrium distributions are considered at low temperatures.The variations of threshold current density in a wide temperature range are analyzed and the negative characteristic temperature and oscillatory characteristic temperature appearing in that temperature range are discussed.Also,the improvement of quantum dot lasers’ performance is investigated through vertical stacking and p-type doping and the optimal dot density,which corresponds to minimal threshold current density, is calculated.

  • Design of an OP-AMP Based on a LDO Regulator

    Fan, Hua, and, Feng, Quanyuan

    Chin. J. Semicond.  2005, 26(10): 1905

    Abstract PDF

    An operational amplifier (OP-AMP) with a ground current of about 0.6μA is presented.Moreover,this amplifier reaps the benefits of incorporating a foldback current limiting circuit,which enables the low-dropout voltage regulator without the need of a special current limiting subblock.Therefore,the object of ultra-low power is realized because of a great reduction in transistors and current limbs.

  • A 2.4GHz Quadrature Output Frequency Synthesizer

    Yi Xiaofeng, Fang Han, Yang Yujia, and Hong Zhiliang

    Chin. J. Semicond.  2005, 26(10): 1910

    Abstract PDF

    A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0.35μm CMOS technology are presented.A differentially controlled quadrature voltage-controlled oscillator (QVCO) is employed to generate quadrature (I/Q) signals.A second-order loop filter,with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost.The measured spot phase noise is –106.15dBc/Hz@1MHz.Close-in phase noise is less than -70dBc/Hz.The synthesizer consumes 13.5mA under a 3.3V voltage supply.The core size is 1.3mm×0.8mm.

  • Temporal Floorplanning Using Solution Space Smoothing Based on 3D-BSSG Structure

    Zheng Shuyi, Dong Sheqin, and Hong Xianlong

    Chin. J. Semicond.  2005, 26(10): 1916

    Abstract PDF

    We develop a 3D bounded slice-surface grid (3D-BSSG) structure for representation and introduce the solution space smoothing technique to search for the optimal solution.Experiment results demonstrate that a 3D-BSSG structure based algorithm is very effective and efficient.

  • 柱型量子点中弱耦合磁极化子的激发态性质

    赵翠兰, 丁朝华, 肖景林

    Chin. J. Semicond.  2005, 26(10): 1925

    Abstract PDF

    应用线性组合算符和幺正变换研究了在量子阱和抛物势作用下的柱型量子点中弱耦合磁极化子的性质. 对AgBr量子点的数值计算表明:量子点中磁极化子的基态能量、激发态能量以及激发能均随特征频率、回旋共振频率的提高而增大;随柱高的减小而增加,且柱高愈小,增加速度愈快;激发态能量随温度的升高而增加. 这些结论说明,由于量子点的受限和磁场的增大以及温度的升高使量子点的极化加强.

  • GaAs-AlxGa1-xAs双势垒结构中电子共振隧穿寿命

    宫箭, 梁希侠, 班士良

    Chin. J. Semicond.  2005, 26(10): 1929

    Abstract PDF

    采用转移矩阵和数值计算相结合的方法求解含时Schrodinger方程,计算了电子在双势垒结构中的构建时间和隧穿寿命. 结果表明:构建时间和隧穿寿命对于描述电子隧穿时间特性同等重要. 通过研究隧穿时间对结构参数的依赖情况发现,隧穿寿命随阱宽和垒厚的增加而迅速增大.

  • (GaN)n/(AlN)n应变层超晶格的电子结构

    王新华, 王玲玲, 王怀玉, 邓辉球, 黄维清

    Chin. J. Semicond.  2005, 26(10): 1934

    Abstract PDF

    以Free-Standing条件生长的超晶格原胞为计算模型,运用LCAO-Recursion方法研究了(GaN)n/(AlN)n (001)应变层超晶格的电子结构. 由计算结果分析了GaN/AlN应变层超晶格中Ga, Al和N之间的成键情况及其带隙Eg随超晶格层数n的变化趋势;当超晶格中存在空位时,带隙中将形成缺陷能级. 最后分析了在超晶格中引入Mg掺杂后对超晶格电子结构的影响.

  • GaN异质结的二维表面态

    薛舫时

    Chin. J. Semicond.  2005, 26(10): 1939

    Abstract PDF

    提出了氮化物表面强极化电荷产生薄吸附层形成的二维表面态新模型. 从薛定谔方程和泊松方程的自洽计算中得到了新的二维表面态. 计算了不同吸附层能带带阶、厚度和表面势下的表面状态,研究了表面态与异质结构间的关联. 算得的表面能级同实验测量数据相吻合. 用该态模型解释了氮化物产生高密度表面态的原因和深表面能级与较浅的瞬态电流激活能间的矛盾.

  • (NH4)2S硫化后ZnS/InP界面的电学特性

    庄春泉, 汤英文, 黄杨程, 吕衍秋, 龚海梅

    Chin. J. Semicond.  2005, 26(10): 1945

    Abstract PDF

    在(NH4)2S硫化后的n-型InP衬底上热蒸发ZnS薄膜制得Au/ZnS/InP(100)MIS器件,测得了其I-V特性曲线以及3MHz下的高频C-V曲线和100Hz下的准静态C-V曲线从这些曲线得到如下结果:正向饱和电流为7e-13A; ZnS钝化下经硫化的n-型InP表面的固定电荷密度为-2.28e11/cm2;禁带中的最低表面态密度约为1e12cm-2·eV-1. 上述结果表明经硫化后的ZnS/InP界面具有良好的界面特性.

  • 导带的非抛物线性对应变InxGa1-xAs/AlAs量子阱红外谱的影响

    杨晓峰, 温廷敦, 张文栋

    Chin. J. Semicond.  2005, 26(10): 1949

    Abstract PDF

    研究了导带非抛物线性对应变In0.84Ga0.16As/AlAs/In0.52Ga0.48As量子阱红外谱的影响. 用8×8 k·p理论分析了导带价带混合引起导带的非抛物线性、费米能级变化和带内跃迁吸收峰位置的改变. 数值分析给出与红外吸收实验相一致的结果,表明导带的非抛物线性对重掺杂量子阱红外谱有显著的影响,从实验红外谱可以推知导带色散的非抛物线性特征.

  • Cu(In,Ga)Se2材料成分对其电池性能的影响

    刘芳芳, 何青, 李凤岩, 敖建平, 孙国忠, 周志强, 孙云

    Chin. J. Semicond.  2005, 26(10): 1954

    Abstract PDF

    利用三步共蒸发法制备铜铟硒薄膜太阳电池中的吸收层CIGS薄膜,采用多种测试手段,研究其成分比例与薄膜的电阻率、载流子浓度、表面粗糙度之间的关系电阻率为1e2~1e3Ω·cm之间,是Cu、III族元素、Se配比较为合适的区域载流子浓度在1e15~1e16cm-3范围内,薄膜表面粗糙度是随着Cu/(Ga+In)比呈下降趋势,Cu越多,表面越光滑,当Cu/(Ga+In)比超过1.25以后,变化趋势逐渐减弱. 当Cu/(Ga+In)比在1.0附近时,粗糙度处于30~60nm之间. 在上述范围内,研制出转换效率为12.1%的CIGS薄膜太阳电池.

  • 拓扑缺陷对碳纳米管电学性能的影响

    张丽芳, 胡慧芳

    Chin. J. Semicond.  2005, 26(10): 1959

    Abstract PDF

    在紧束缚近似基础上,利用扩展的Su-Schriffer-Heeger (SSH)模型,在实空间中计算了理想的“zigzag”碳纳米管中分别引入5/7, 5/6/7, 5/6/6/7拓扑缺陷所构成的(9,0)-(8,0), (9,0)-(7,0)和(9,0)-(6,0)三种系统的能带结构和电荷密度,并对这三种系统的计算结果进行了比较. 结果表明,拓扑缺陷五边形和七边形在碳管中沿轴向的不同分布对碳管电学性能的影响明显不同. 因此,可以研制出基于这些异质结的不同电子器件基元.

  • ZnO/p-Si异质结的光电转换特性

    段理, 林碧霞, 傅竹西, 蔡俊江, 张子俞

    Chin. J. Semicond.  2005, 26(10): 1963

    Abstract PDF

    通过直流反应溅射制备了整流特性良好的ZnO/p-Si异质结,并在该异质结上观察到了明显的光电转换特性. 研究表明ZnO薄膜中的电子浓度在一个合适的数值(1.6e15cm-3)时光电流最强,另外晶粒尺寸越大光电流越强. 分析表明,电子浓度和晶粒直径对光电流的影响规律在很大程度上是载流子散射导致的. 此外,还发现ZnO薄膜存在一个临界厚度,当薄膜厚度大于该临界厚度时,异质结的光电压和光电流都急剧衰减并很快接近于0. 实验表明,这个临界厚度和ZnO薄膜(001)面最大晶粒直径一致.

  • TLP应力下深亚微米GGNMOSFET特性的仿真

    朱志炜, 郝跃

    Chin. J. Semicond.  2005, 26(10): 1968

    Abstract PDF

    对TLP(传输线脉冲)应力下深亚微米GGNMOS器件的特性和失效机理进行了仿真研究. 分析表明,在TLP应力下,栅串接电阻减小了保护结构漏端的峰值电压;栅漏交迭区电容的存在使得脉冲上升沿加强了栅漏交叠区的电场,栅氧化层电场随着TLP应力的上升沿减小而不断增大,这会导致栅氧化层的提前击穿. 仿真显示,栅漏交迭区的电容和栅串接电阻对GGNMOS保护器件的开启特性和ESD耐压的影响是巨大的. 该工作为以后的TLP测试和标准化提供了依据和参考.

  • MOS结构热载子注入与总剂量辐照响应的相关性

    余学峰, 任迪远, 艾尔肯, 张国强, 陆妩, 郭旗

    Chin. J. Semicond.  2005, 26(10): 1975

    Abstract PDF

    通过对MOS电容进行热载子注入和总剂量辐照实验,探讨了MOS结构热载子注入与总剂量辐射响应的相关性. 研究结果表明,热载子注入和总剂量辐射都会引起MOS结构的损伤,但前者产生的损伤是由于热电子注入在MOS结构的Si/SiO2系统引入氧化物负电荷引起的,后者产生的损伤是由于电离辐射在MOS结构的Si/SiO2系统感生氧化物正电荷和界面态而导致的. 进一步的研究表明,针对总剂量辐射损伤采用的加固工艺,能对热电子注入感生氧化物负电荷起到非常有效的抑制作用.

  • 八羟基喹啉锌非晶薄膜器件的制备和开关特性

    时军朋, 温振超, 宋长安, 陈殷, 彭应全

    Chin. J. Semicond.  2005, 26(10): 1979

    Abstract PDF

    介绍了八羟基喹啉锌(Znq2)有机薄膜及器件的制备方法. X射线衍射谱指出,用真空蒸发方法制备的Znq2薄膜呈非晶态结构;通过对Znq2有机薄膜I-V曲线的分析,揭示了Znq2薄膜的开关特性. 基于分子在电场作用下的空间取向的变化,对这一现象提出了一种可能的理论解释.

  • 用阱作高阻漂移区的LDMOS导通电阻的解析模型

    孟坚, 高珊, 陈军宁, 柯导明, 孙伟锋, 时龙兴, 徐超

    Chin. J. Semicond.  2005, 26(10): 1983

    Abstract PDF

    分析了一个用阱作为耐高压漂移区的LDMOS的导通电阻,提出了带有场极板的高阻漂移区导通电阻的计算公式,改进了双扩散沟道导通电阻的计算公式. 针对一个LDMOS的例子做了计算,并将其与相同参数情况下用MEDICI软件模拟的结果作了对比. 结果表明两者相差仅5%,这说明所得公式可用于该类型LDMOS的分析和设计.

  • 用于40Gb/s光接收机的0.2μm GaAs PHEMT分布放大器

    郑远, 陈堂胜, 钱峰, 李拂晓, 邵凯

    Chin. J. Semicond.  2005, 26(10): 1989

    Abstract PDF

    利用0.2μm GaAs PHEMT工艺实现了40Gb/s光接收机中的前置放大器. 该放大器采用有源偏置的七级分布放大器结构,3dB带宽超过40GHz,输入输出反射损耗小于-10dB,跨阻增益为45.6dBΩ,最小等效输入噪声电流密度为22pA/Hz,功耗为300mW,可有效地应用于40Gb/s光接收机中.

  • MS/RF CMOS工艺兼容的光电探测器

    黄家乐, 毛陆虹, 陈弘达, 高鹏, 刘金彬, 雷晓荃

    Chin. J. Semicond.  2005, 26(10): 1995

    Abstract PDF

    为实现光纤通信系统中的单片光电集成,采用工业标准工艺设计了硅基光电探测器,讨论了光电探测器的机理,提出了五种新的探测器结构,并采用TSMC 0.18μm MS/RF CMOS工艺进行了流片. 利用半导体测试仪对芯片进行了测试,包括探测器的暗电流、响应度和结电容,并分析了深n阱、浅沟槽隔离等工艺步骤对探测器参数的影响. 结果表明,利用标准MS/RF CMOS工艺实现的光电探测器具有良好的特性.

  • 用于40Gb/s光电子器件的新型低成本硅基过渡热沉

    熊兵, 王健, 蔡鹏飞, 田建柏, 孙长征, 罗毅

    Chin. J. Semicond.  2005, 26(10): 2001

    Abstract PDF

    提出了一种新型低成本硅基过渡热沉,用以实现高达40Gb/s的高速光电子器件封装. 采用高阻硅衬底作为热沉基底,制作出了0~40GHz范围内传输损耗小于0.165dB/mm的共面波导传输线. 热沉中采用Ta2N薄膜电阻作为负载以实现器件的阻抗匹配,达到了0~40GHz范围内低于-18dB的宽带低反射特性. 和传统硅基平台相比,新型硅基热沉更具有制作工艺简单、导热性能良好等优点. 为了证明其实用性,热沉被应用于高速电吸收调制器的管芯级封装测试,获得了超过33GHz的小信号调制带宽特性,在硅基热沉上首次实现可用于40Gb/s系统的光电子器件.

  • 一种改进的CMOS差分LC压控振荡器

    李永峰, 张建辉

    Chin. J. Semicond.  2005, 26(10): 2006

    Abstract PDF

    介绍了一种改进的LC振荡器设计方法.谐振回路采用非对称电容结构,与常见的振荡器结构相比,经改进后的电路结构可以获得更好的相位噪声.基于0.35μm CMOS工艺,设计了一种采用补偿Colpitts振荡器电路结构实现的差分LC压控振荡器,工作电压为2.5V.经仿真证明,在设计中通过调整非对称电容谐振回路中的电容值,可以获得最优的相位噪声.

  • 一种采用开关阶跃电容的压控振荡器(上):调谐特性的理论分析

    唐长文, 何捷, 闵昊

    Chin. J. Semicond.  2005, 26(10): 2010

    Abstract PDF

    针对采用阶跃可变电容的电感电容压控振荡器电路,本文提出了一种振荡器调谐特性的时域分析方法--周期计算技术. 通过对电感电容谐振回路中电感的I-V曲线分析,详细地阐述了阶跃可变电容能够实现线性压控的物理机理和本质. 对差分调谐电感电容压控振荡器的调谐特性也进行了详细的分析. SPICE电路仿真验证了调谐特性理论分析的正确性.

  • 低压低功耗CMOS带隙电压基准及启动电路设计

    许长喜

    Chin. J. Semicond.  2005, 26(10): 2022

    Abstract PDF

    介绍了一种低压电流模带隙电压基准电路,并提出了一种新颖的启动电路结构. 电路采用预先设置电路工作点和反馈控制相结合的方法有效地克服了第三简并点的问题,从而保证电路能够正常工作. 文中给出详细的分析和电路实现,并给出了一种电路简并点和启动裕度分析的SPICE仿真方法. 电路采用0.25μm CMOS工艺设计并流片. 最后对电路的测试结果进行了比较和分析.

  • LDMOS低功耗自恢复电平移位电路设计

    邓兰萍, 王纪民

    Chin. J. Semicond.  2005, 26(10): 2028

    Abstract PDF

    设计了一个新型的薄栅氧、低功耗、自恢复的电平移位栅电压控制电路. 在20V工作电压下,n沟道和p沟道LDMOS高压器件的栅源电压Vgs分别保持在±5V. 当一个选址周期结束后,电路能自动复位而不需增加任何复位器件和电路. 该电路为高低压兼容,采用标准0.5μm CMOS-LDMOS兼容工艺制造,可用于OLED显示的驱动控制.

  • 表征ULSI低介电常数互连材料机械特性的表面波频散特性

    李志国, 肖夏, 张鑫慧, 姚素英

    Chin. J. Semicond.  2005, 26(10): 2032

    Abstract PDF

    研究了在Si(100)衬底上淀积低k薄膜的分层结构中表面波沿Si[100]和[110]晶向传播的速度-频率色散特性,给出了表面波色散特性的理论推导,得到了低k薄膜的杨氏模量、密度、厚度和泊松常数对色散关系的影响.

  • 深亚微米HCI模型参数多目标全域提取方法

    李康, 郝跃, 刘红侠, 马晓华, 马佩军

    Chin. J. Semicond.  2005, 26(10): 2038

    Abstract PDF

    研究了一种建立在退化栅电流物理解析模型基础上的深亚微米pMOS器件HCI(hot carrier injection)退化模型. 提出了一种基于L-M (Levenberg-Marquardt)算法的多目标响应全域优化提取策略,并对可靠性模型参数进行优化提取. 分析了优化过程中由于参数灵敏度过低产生的问题并提出采用递归算法求解不同时刻栅电流注入电荷量的加速计算方法. 最后,给出了最优化参数提取的结果,并且将测量值与理论值进行了比较,得到很好的一致性.

  • 128×160元GaAs/AlGaAs多量子阱长波红外焦平面阵列

    苏艳梅, 种明, 张艳冰, 胡小燕, 孙永伟, 赵伟, 陈良惠

    Chin. J. Semicond.  2005, 26(10): 2044

    Abstract PDF

    研制了128×160元GaAs/AlGaAs多量子阱红外焦平面阵列,它是目前国内报道的最大像元数的量子阱红外焦平面阵列. 77K时,器件的平均黑体响应率Rv=2.81e7V/W,平均峰值探测率Dλ=1.28e10cm·W-1·Hz1/2,峰值波长λp=8.1μm,器件的盲元率为1.22%.

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